Lines Matching refs:RCS0
49 {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
50 {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
51 {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
52 {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
53 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
54 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
55 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
56 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
57 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
58 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
59 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
60 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
61 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
62 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
63 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
64 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
65 {RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
66 {RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
67 {RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
68 {RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
69 {RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
70 {RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
77 {RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */
81 {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
82 {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
83 {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
84 {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
85 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
86 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
87 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
88 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
89 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
90 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
91 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
92 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
93 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
94 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
95 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
96 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
97 {RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
98 {RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
99 {RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
100 {RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
101 {RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
102 {RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
104 {RCS0, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */
105 {RCS0, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */
106 {RCS0, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */
107 {RCS0, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */
108 {RCS0, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */
109 {RCS0, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */
110 {RCS0, GEN9_SCRATCH1, 0, false}, /* 0xb11c */
111 {RCS0, GEN9_SCRATCH_LNCF1, 0, false}, /* 0xb008 */
112 {RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
113 {RCS0, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
114 {RCS0, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
115 {RCS0, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
116 {RCS0, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
117 {RCS0, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
118 {RCS0, TRVATTL3PTRDW(0), 0, true}, /* 0x4de0 */
119 {RCS0, TRVATTL3PTRDW(1), 0, true}, /* 0x4de4 */
120 {RCS0, TRNULLDETCT, 0, true}, /* 0x4de8 */
121 {RCS0, TRINVTILEDETCT, 0, true}, /* 0x4dec */
122 {RCS0, TRVADR, 0, true}, /* 0x4df0 */
123 {RCS0, TRTTE, 0, true}, /* 0x4df4 */
124 {RCS0, _MMIO(0x4dfc), 0, true},
136 {RCS0, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */
137 {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
138 {RCS0, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */
139 {RCS0, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */
141 {RCS0, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
142 {RCS0, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */
143 {RCS0, _MMIO(0x20D8), 0xffff, true}, /* 0x20d8 */
145 {RCS0, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
146 {RCS0, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
147 {RCS0, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */
148 {RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */
158 [RCS0] = 0xc800,
321 if (req->engine->id != RCS0) in intel_vgpu_restore_inhibit_context()
345 [RCS0] = 0x4260,
380 if (engine->id == RCS0 && GRAPHICS_VER(engine->i915) >= 9) in handle_tlb_pending_event()
402 [RCS0] = 0xc800, in switch_mocs()
416 if (engine->id == RCS0 && GRAPHICS_VER(engine->i915) == 9) in switch_mocs()
439 if (engine->id == RCS0) { in switch_mocs()