2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
53 	struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;  in edid_get_byte()  local
56 	if (edid->state == I2C_NOT_SPECIFIED || !edid->slave_selected) {  in edid_get_byte()
57 		gvt_vgpu_err("Driver tries to read EDID without proper sequence!\n");  in edid_get_byte()
60 	if (edid->current_edid_read >= EDID_SIZE) {  in edid_get_byte()
61 		gvt_vgpu_err("edid_get_byte() exceeds the size of EDID!\n");  in edid_get_byte()
65 	if (!edid->edid_available) {  in edid_get_byte()
66 		gvt_vgpu_err("Reading EDID but EDID is not available!\n");  in edid_get_byte()
70 	if (intel_vgpu_has_monitor_on_port(vgpu, edid->port)) {  in edid_get_byte()
72 			intel_vgpu_port(vgpu, edid->port)->edid;  in edid_get_byte()
74 		chr = edid_data->edid_block[edid->current_edid_read];  in edid_get_byte()
75 		edid->current_edid_read++;  in edid_get_byte()
77 		gvt_vgpu_err("No EDID available during the reading?\n");  in edid_get_byte()
85 	int port = -EINVAL;  in cnp_get_port_from_gmbus0()
101 	int port = -EINVAL;  in bxt_get_port_from_gmbus0()
115 	int port = -EINVAL;  in get_port_from_gmbus0()
131 	if (!vgpu->display.i2c_edid.edid_available)  in reset_gmbus_controller()
133 	vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;  in reset_gmbus_controller()
140 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;  in gmbus0_mmio_write()
158 	if (drm_WARN_ON(&i915->drm, port < 0))  in gmbus0_mmio_write()
161 	vgpu->display.i2c_edid.state = I2C_GMBUS;  in gmbus0_mmio_write()
162 	vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;  in gmbus0_mmio_write()
169 		vgpu->display.i2c_edid.port = port;  in gmbus0_mmio_write()
170 		vgpu->display.i2c_edid.edid_available = true;  in gmbus0_mmio_write()
180 	struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;  in gmbus1_mmio_write()
210 		i2c_edid->gmbus.total_byte_count =  in gmbus1_mmio_write()
214 		/* vgpu gmbus only support EDID */  in gmbus1_mmio_write()
216 			i2c_edid->slave_selected = true;  in gmbus1_mmio_write()
221 					vgpu->id, slave_addr);  in gmbus1_mmio_write()
225 			i2c_edid->current_edid_read =  in gmbus1_mmio_write()
228 		i2c_edid->gmbus.cycle_type = gmbus1_bus_cycle(wvalue);  in gmbus1_mmio_write()
244 				 * few milliseconds. In emulation, we just set  in gmbus1_mmio_write()
248 				i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;  in gmbus1_mmio_write()
258 			 * START (-->INDEX) -->DATA  in gmbus1_mmio_write()
260 			i2c_edid->gmbus.phase = GMBUS_DATA_PHASE;  in gmbus1_mmio_write()
281 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;  in gmbus3_mmio_write()
283 	drm_WARN_ON(&i915->drm, 1);  in gmbus3_mmio_write()
292 	struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;  in gmbus3_mmio_read()
293 	int byte_left = i2c_edid->gmbus.total_byte_count -  in gmbus3_mmio_read()
294 				i2c_edid->current_edid_read;  in gmbus3_mmio_read()
316 			switch (i2c_edid->gmbus.cycle_type) {  in gmbus3_mmio_read()
319 				i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;  in gmbus3_mmio_read()
324 				i2c_edid->gmbus.phase = GMBUS_WAIT_PHASE;  in gmbus3_mmio_read()
358 	/* All other bits are read-only */  in gmbus2_mmio_write()
363  * intel_gvt_i2c_handle_gmbus_read - emulate gmbus register mmio read
378 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;  in intel_gvt_i2c_handle_gmbus_read()
380 	if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))  in intel_gvt_i2c_handle_gmbus_read()
381 		return -EINVAL;  in intel_gvt_i2c_handle_gmbus_read()
393  * intel_gvt_i2c_handle_gmbus_write - emulate gmbus register mmio write
408 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;  in intel_gvt_i2c_handle_gmbus_write()
410 	if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))  in intel_gvt_i2c_handle_gmbus_write()
411 		return -EINVAL;  in intel_gvt_i2c_handle_gmbus_write()
459 		reg = -1;  in get_aux_ch_reg()
470  * intel_gvt_i2c_handle_aux_ch_write - emulate AUX channel register write
484 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;  in intel_gvt_i2c_handle_aux_ch_write()
485 	struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;  in intel_gvt_i2c_handle_aux_ch_write()
521 			i2c_edid->aux_ch.i2c_over_aux_ch = true;  in intel_gvt_i2c_handle_aux_ch_write()
522 			i2c_edid->aux_ch.aux_ch_mot = true;  in intel_gvt_i2c_handle_aux_ch_write()
527 				i2c_edid->state = I2C_AUX_CH;  in intel_gvt_i2c_handle_aux_ch_write()
528 				i2c_edid->port = port_idx;  in intel_gvt_i2c_handle_aux_ch_write()
529 				i2c_edid->slave_selected = true;  in intel_gvt_i2c_handle_aux_ch_write()
533 					i2c_edid->edid_available = true;  in intel_gvt_i2c_handle_aux_ch_write()
538 		 * We only support EDID reading from I2C_over_AUX. And  in intel_gvt_i2c_handle_aux_ch_write()
541 		 * support the gfx driver to do EDID access.  in intel_gvt_i2c_handle_aux_ch_write()
544 		if (drm_WARN_ON(&i915->drm, (op & 0x1) != GVT_AUX_I2C_READ))  in intel_gvt_i2c_handle_aux_ch_write()
546 		if (drm_WARN_ON(&i915->drm, msg_length != 4))  in intel_gvt_i2c_handle_aux_ch_write()
548 		if (i2c_edid->edid_available && i2c_edid->slave_selected) {  in intel_gvt_i2c_handle_aux_ch_write()
564  * intel_vgpu_init_i2c_edid - initialize vGPU i2c edid emulation
567  * This function is used to initialize vGPU i2c edid emulation stuffs
572 	struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;  in intel_vgpu_init_i2c_edid()  local
574 	edid->state = I2C_NOT_SPECIFIED;  in intel_vgpu_init_i2c_edid()
576 	edid->port = -1;  in intel_vgpu_init_i2c_edid()
577 	edid->slave_selected = false;  in intel_vgpu_init_i2c_edid()
578 	edid->edid_available = false;  in intel_vgpu_init_i2c_edid()
579 	edid->current_edid_read = 0;  in intel_vgpu_init_i2c_edid()
581 	memset(&edid->gmbus, 0, sizeof(struct intel_vgpu_i2c_gmbus));  in intel_vgpu_init_i2c_edid()
583 	edid->aux_ch.i2c_over_aux_ch = false;  in intel_vgpu_init_i2c_edid()
584 	edid->aux_ch.aux_ch_mot = false;  in intel_vgpu_init_i2c_edid()