Lines Matching +full:cs +full:- +full:2
1 // SPDX-License-Identifier: MIT
26 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
28 #define NUM_GPR_DW (NUM_GPR * 2) /* each GPR is 2 dwords */
35 return __vm_create_scratch_for_read_pinned(>->ggtt->vm, PAGE_SIZE); in create_scratch()
57 tasklet_hi_schedule(&engine->sched_engine->tasklet); in wait_for_submit()
68 if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) in wait_for_submit()
72 return -ETIME; in wait_for_submit()
81 i915_ggtt_offset(ce->engine->status_page.vma) + in emit_semaphore_signal()
84 u32 *cs; in emit_semaphore_signal() local
90 cs = intel_ring_begin(rq, 4); in emit_semaphore_signal()
91 if (IS_ERR(cs)) { in emit_semaphore_signal()
93 return PTR_ERR(cs); in emit_semaphore_signal()
96 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; in emit_semaphore_signal()
97 *cs++ = offset; in emit_semaphore_signal()
98 *cs++ = 0; in emit_semaphore_signal()
99 *cs++ = 1; in emit_semaphore_signal()
101 intel_ring_advance(rq, cs); in emit_semaphore_signal()
103 rq->sched.attr.priority = I915_PRIORITY_BARRIER; in emit_semaphore_signal()
114 rq = intel_engine_create_kernel_request(ce->engine); in context_flush()
118 fence = i915_active_fence_get(&ce->timeline->last_request); in context_flush()
127 err = -ETIME; in context_flush()
139 if (GRAPHICS_VER(engine->i915) < 12) in get_lri_mask()
142 switch (engine->class) { in get_lri_mask()
170 return -ENOMEM; in live_lrc_layout()
178 if (!engine->default_state) in live_lrc_layout()
181 hw = shmem_pin_map(engine->default_state); in live_lrc_layout()
183 err = -ENOMEM; in live_lrc_layout()
189 engine->kernel_context, engine, true); in live_lrc_layout()
203 engine->name, lri, dw); in live_lrc_layout()
210 engine->name, dw, lri); in live_lrc_layout()
211 err = -EINVAL; in live_lrc_layout()
217 engine->name, dw, lri, lrc[dw]); in live_lrc_layout()
218 err = -EINVAL; in live_lrc_layout()
228 * RCS && CCS: BITS(0 - 10) in live_lrc_layout()
229 * BCS: BITS(0 - 11) in live_lrc_layout()
230 * VECS && VCS: BITS(0 - 13) in live_lrc_layout()
243 engine->name, dw, offset, lrc[dw]); in live_lrc_layout()
244 err = -EINVAL; in live_lrc_layout()
252 dw += 2; in live_lrc_layout()
253 lri -= 2; in live_lrc_layout()
258 pr_info("%s: HW register image:\n", engine->name); in live_lrc_layout()
261 pr_info("%s: SW register image:\n", engine->name); in live_lrc_layout()
265 shmem_unpin_map(engine->default_state, hw); in live_lrc_layout()
282 return -1; in find_offset()
304 i915_mmio_reg_offset(RING_START(engine->mmio_base)), in live_lrc_fixed()
305 CTX_RING_START - 1, in live_lrc_fixed()
309 i915_mmio_reg_offset(RING_CTL(engine->mmio_base)), in live_lrc_fixed()
310 CTX_RING_CTL - 1, in live_lrc_fixed()
314 i915_mmio_reg_offset(RING_HEAD(engine->mmio_base)), in live_lrc_fixed()
315 CTX_RING_HEAD - 1, in live_lrc_fixed()
319 i915_mmio_reg_offset(RING_TAIL(engine->mmio_base)), in live_lrc_fixed()
320 CTX_RING_TAIL - 1, in live_lrc_fixed()
324 i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)), in live_lrc_fixed()
329 i915_mmio_reg_offset(RING_BBSTATE(engine->mmio_base)), in live_lrc_fixed()
330 CTX_BB_STATE - 1, in live_lrc_fixed()
334 i915_mmio_reg_offset(RING_BB_PER_CTX_PTR(engine->mmio_base)), in live_lrc_fixed()
339 i915_mmio_reg_offset(RING_INDIRECT_CTX(engine->mmio_base)), in live_lrc_fixed()
344 i915_mmio_reg_offset(RING_INDIRECT_CTX_OFFSET(engine->mmio_base)), in live_lrc_fixed()
349 i915_mmio_reg_offset(RING_CTX_TIMESTAMP(engine->mmio_base)), in live_lrc_fixed()
350 CTX_TIMESTAMP - 1, in live_lrc_fixed()
354 i915_mmio_reg_offset(GEN8_RING_CS_GPR(engine->mmio_base, 0)), in live_lrc_fixed()
359 i915_mmio_reg_offset(RING_CMD_BUF_CCTL(engine->mmio_base)), in live_lrc_fixed()
364 i915_mmio_reg_offset(RING_BB_OFFSET(engine->mmio_base)), in live_lrc_fixed()
372 if (!engine->default_state) in live_lrc_fixed()
375 hw = shmem_pin_map(engine->default_state); in live_lrc_fixed()
377 err = -ENOMEM; in live_lrc_fixed()
382 for (t = tbl; t->name; t++) { in live_lrc_fixed()
383 int dw = find_offset(hw, t->reg); in live_lrc_fixed()
385 if (dw != t->offset) { in live_lrc_fixed()
387 engine->name, in live_lrc_fixed()
388 t->name, in live_lrc_fixed()
389 t->reg, in live_lrc_fixed()
391 t->offset); in live_lrc_fixed()
392 err = -EINVAL; in live_lrc_fixed()
396 shmem_unpin_map(engine->default_state, hw); in live_lrc_fixed()
414 u32 *cs; in __live_lrc_state() local
424 err = i915_gem_object_lock(scratch->obj, &ww); in __live_lrc_state()
436 cs = intel_ring_begin(rq, 4 * MAX_IDX); in __live_lrc_state()
437 if (IS_ERR(cs)) { in __live_lrc_state()
438 err = PTR_ERR(cs); in __live_lrc_state()
443 *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT; in __live_lrc_state()
444 *cs++ = i915_mmio_reg_offset(RING_START(engine->mmio_base)); in __live_lrc_state()
445 *cs++ = i915_ggtt_offset(scratch) + RING_START_IDX * sizeof(u32); in __live_lrc_state()
446 *cs++ = 0; in __live_lrc_state()
448 expected[RING_START_IDX] = i915_ggtt_offset(ce->ring->vma); in __live_lrc_state()
450 *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT; in __live_lrc_state()
451 *cs++ = i915_mmio_reg_offset(RING_TAIL(engine->mmio_base)); in __live_lrc_state()
452 *cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32); in __live_lrc_state()
453 *cs++ = 0; in __live_lrc_state()
455 err = i915_request_await_object(rq, scratch->obj, true); in __live_lrc_state()
465 expected[RING_TAIL_IDX] = ce->ring->tail; in __live_lrc_state()
468 err = -ETIME; in __live_lrc_state()
472 cs = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB); in __live_lrc_state()
473 if (IS_ERR(cs)) { in __live_lrc_state()
474 err = PTR_ERR(cs); in __live_lrc_state()
479 if (cs[n] != expected[n]) { in __live_lrc_state()
481 engine->name, n, cs[n], expected[n]); in __live_lrc_state()
482 err = -EINVAL; in __live_lrc_state()
487 i915_gem_object_unpin_map(scratch->obj); in __live_lrc_state()
494 if (err == -EDEADLK) { in __live_lrc_state()
527 if (igt_flush_test(gt->i915)) in live_lrc_state()
528 err = -EIO; in live_lrc_state()
537 u32 *cs; in gpr_make_dirty() local
544 cs = intel_ring_begin(rq, 2 * NUM_GPR_DW + 2); in gpr_make_dirty()
545 if (IS_ERR(cs)) { in gpr_make_dirty()
547 return PTR_ERR(cs); in gpr_make_dirty()
550 *cs++ = MI_LOAD_REGISTER_IMM(NUM_GPR_DW); in gpr_make_dirty()
552 *cs++ = CS_GPR(ce->engine, n); in gpr_make_dirty()
553 *cs++ = STACK_MAGIC; in gpr_make_dirty()
555 *cs++ = MI_NOOP; in gpr_make_dirty()
557 intel_ring_advance(rq, cs); in gpr_make_dirty()
559 rq->sched.attr.priority = I915_PRIORITY_BARRIER; in gpr_make_dirty()
569 i915_ggtt_offset(ce->engine->status_page.vma) + in __gpr_read()
572 u32 *cs; in __gpr_read() local
580 cs = intel_ring_begin(rq, 6 + 4 * NUM_GPR_DW); in __gpr_read()
581 if (IS_ERR(cs)) { in __gpr_read()
583 return ERR_CAST(cs); in __gpr_read()
586 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; in __gpr_read()
587 *cs++ = MI_NOOP; in __gpr_read()
589 *cs++ = MI_SEMAPHORE_WAIT | in __gpr_read()
593 *cs++ = 0; in __gpr_read()
594 *cs++ = offset; in __gpr_read()
595 *cs++ = 0; in __gpr_read()
598 *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT; in __gpr_read()
599 *cs++ = CS_GPR(ce->engine, n); in __gpr_read()
600 *cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32); in __gpr_read()
601 *cs++ = 0; in __gpr_read()
605 err = i915_request_await_object(rq, scratch->obj, true); in __gpr_read()
624 u32 *slot = memset32(engine->status_page.addr + 1000, 0, 4); in __live_lrc_gpr()
627 u32 *cs; in __live_lrc_gpr() local
631 if (GRAPHICS_VER(engine->i915) < 9 && engine->class != RENDER_CLASS) in __live_lrc_gpr()
634 err = gpr_make_dirty(engine->kernel_context); in __live_lrc_gpr()
648 err = wait_for_submit(engine, rq, HZ / 2); in __live_lrc_gpr()
653 err = gpr_make_dirty(engine->kernel_context); in __live_lrc_gpr()
657 err = emit_semaphore_signal(engine->kernel_context, slot); in __live_lrc_gpr()
661 err = wait_for_submit(engine, rq, HZ / 2); in __live_lrc_gpr()
670 err = -ETIME; in __live_lrc_gpr()
674 cs = i915_gem_object_pin_map_unlocked(scratch->obj, I915_MAP_WB); in __live_lrc_gpr()
675 if (IS_ERR(cs)) { in __live_lrc_gpr()
676 err = PTR_ERR(cs); in __live_lrc_gpr()
681 if (cs[n]) { in __live_lrc_gpr()
683 engine->name, in __live_lrc_gpr()
684 n / 2, n & 1 ? "udw" : "ldw", in __live_lrc_gpr()
685 cs[n]); in __live_lrc_gpr()
686 err = -EINVAL; in __live_lrc_gpr()
691 i915_gem_object_unpin_map(scratch->obj); in __live_lrc_gpr()
694 memset32(&slot[0], -1, 4); in __live_lrc_gpr()
732 if (igt_flush_test(gt->i915)) in live_lrc_gpr()
733 err = -EIO; in live_lrc_gpr()
746 i915_ggtt_offset(ce->engine->status_page.vma) + in create_timestamp()
749 u32 *cs; in create_timestamp() local
756 cs = intel_ring_begin(rq, 10); in create_timestamp()
757 if (IS_ERR(cs)) { in create_timestamp()
758 err = PTR_ERR(cs); in create_timestamp()
762 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; in create_timestamp()
763 *cs++ = MI_NOOP; in create_timestamp()
765 *cs++ = MI_SEMAPHORE_WAIT | in create_timestamp()
769 *cs++ = 0; in create_timestamp()
770 *cs++ = offset; in create_timestamp()
771 *cs++ = 0; in create_timestamp()
773 *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT; in create_timestamp()
774 *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(rq->engine->mmio_base)); in create_timestamp()
775 *cs++ = offset + idx * sizeof(u32); in create_timestamp()
776 *cs++ = 0; in create_timestamp()
778 intel_ring_advance(rq, cs); in create_timestamp()
794 struct intel_context *ce[2];
800 return (s32)(end - start) > 0; in timestamp_advanced()
805 u32 *slot = memset32(arg->engine->status_page.addr + 1000, 0, 4); in __lrc_timestamp()
810 arg->ce[0]->lrc_reg_state[CTX_TIMESTAMP] = arg->poison; in __lrc_timestamp()
811 rq = create_timestamp(arg->ce[0], slot, 1); in __lrc_timestamp()
815 err = wait_for_submit(rq->engine, rq, HZ / 2); in __lrc_timestamp()
820 arg->ce[1]->lrc_reg_state[CTX_TIMESTAMP] = 0xdeadbeef; in __lrc_timestamp()
821 err = emit_semaphore_signal(arg->ce[1], slot); in __lrc_timestamp()
830 err = context_flush(arg->ce[0], HZ / 2); in __lrc_timestamp()
834 if (!timestamp_advanced(arg->poison, slot[1])) { in __lrc_timestamp()
836 arg->engine->name, preempt ? "preempt" : "simple", in __lrc_timestamp()
837 arg->poison, slot[1]); in __lrc_timestamp()
838 err = -EINVAL; in __lrc_timestamp()
841 timestamp = READ_ONCE(arg->ce[0]->lrc_reg_state[CTX_TIMESTAMP]); in __lrc_timestamp()
844 arg->engine->name, preempt ? "preempt" : "simple", in __lrc_timestamp()
846 err = -EINVAL; in __lrc_timestamp()
850 memset32(slot, -1, 4); in __lrc_timestamp()
921 if (igt_flush_test(gt->i915)) in live_lrc_timestamp()
922 err = -EIO; in live_lrc_timestamp()
937 obj = i915_gem_object_create_internal(vm->i915, size); in create_user_vma()
973 u32 dw, x, *cs, *hw; in store_context() local
976 batch = create_user_vma(ce->vm, SZ_64K); in store_context()
980 cs = i915_gem_object_pin_map_unlocked(batch->obj, I915_MAP_WC); in store_context()
981 if (IS_ERR(cs)) { in store_context()
983 return ERR_CAST(cs); in store_context()
986 defaults = shmem_pin_map(ce->engine->default_state); in store_context()
988 i915_gem_object_unpin_map(batch->obj); in store_context()
990 return ERR_PTR(-ENOMEM); in store_context()
1021 dw += len + 2; in store_context()
1027 ce->engine->name); in store_context()
1033 len = (len + 1) / 2; in store_context()
1034 while (len--) { in store_context()
1035 *cs++ = MI_STORE_REGISTER_MEM_GEN8; in store_context()
1036 *cs++ = hw[dw]; in store_context()
1037 *cs++ = lower_32_bits(scratch->node.start + x); in store_context()
1038 *cs++ = upper_32_bits(scratch->node.start + x); in store_context()
1040 dw += 2; in store_context()
1046 *cs++ = MI_BATCH_BUFFER_END; in store_context()
1048 shmem_unpin_map(ce->engine->default_state, defaults); in store_context()
1050 i915_gem_object_flush_map(batch->obj); in store_context()
1051 i915_gem_object_unpin_map(batch->obj); in store_context()
1063 err = i915_request_await_object(rq, vma->obj, flags); in move_to_active()
1079 u32 *cs; in record_registers() local
1112 cs = intel_ring_begin(rq, 14); in record_registers()
1113 if (IS_ERR(cs)) { in record_registers()
1114 err = PTR_ERR(cs); in record_registers()
1118 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; in record_registers()
1119 *cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8); in record_registers()
1120 *cs++ = lower_32_bits(b_before->node.start); in record_registers()
1121 *cs++ = upper_32_bits(b_before->node.start); in record_registers()
1123 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; in record_registers()
1124 *cs++ = MI_SEMAPHORE_WAIT | in record_registers()
1128 *cs++ = 0; in record_registers()
1129 *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) + in record_registers()
1131 *cs++ = 0; in record_registers()
1132 *cs++ = MI_NOOP; in record_registers()
1134 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; in record_registers()
1135 *cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8); in record_registers()
1136 *cs++ = lower_32_bits(b_after->node.start); in record_registers()
1137 *cs++ = upper_32_bits(b_after->node.start); in record_registers()
1139 intel_ring_advance(rq, cs); in record_registers()
1159 u32 dw, *cs, *hw; in load_context() local
1162 batch = create_user_vma(ce->vm, SZ_64K); in load_context()
1166 cs = i915_gem_object_pin_map_unlocked(batch->obj, I915_MAP_WC); in load_context()
1167 if (IS_ERR(cs)) { in load_context()
1169 return ERR_CAST(cs); in load_context()
1172 defaults = shmem_pin_map(ce->engine->default_state); in load_context()
1174 i915_gem_object_unpin_map(batch->obj); in load_context()
1176 return ERR_PTR(-ENOMEM); in load_context()
1195 dw += len + 2; in load_context()
1201 ce->engine->name); in load_context()
1207 len = (len + 1) / 2; in load_context()
1208 *cs++ = MI_LOAD_REGISTER_IMM(len); in load_context()
1209 while (len--) { in load_context()
1210 *cs++ = hw[dw]; in load_context()
1211 *cs++ = safe_poison(hw[dw] & get_lri_mask(ce->engine, in load_context()
1214 dw += 2; in load_context()
1219 *cs++ = MI_BATCH_BUFFER_END; in load_context()
1221 shmem_unpin_map(ce->engine->default_state, defaults); in load_context()
1223 i915_gem_object_flush_map(batch->obj); in load_context()
1224 i915_gem_object_unpin_map(batch->obj); in load_context()
1233 u32 *cs; in poison_registers() local
1250 cs = intel_ring_begin(rq, 8); in poison_registers()
1251 if (IS_ERR(cs)) { in poison_registers()
1252 err = PTR_ERR(cs); in poison_registers()
1256 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; in poison_registers()
1257 *cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8); in poison_registers()
1258 *cs++ = lower_32_bits(batch->node.start); in poison_registers()
1259 *cs++ = upper_32_bits(batch->node.start); in poison_registers()
1261 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; in poison_registers()
1262 *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) + in poison_registers()
1264 *cs++ = 0; in poison_registers()
1265 *cs++ = 1; in poison_registers()
1267 intel_ring_advance(rq, cs); in poison_registers()
1269 rq->sched.attr.priority = I915_PRIORITY_BARRIER; in poison_registers()
1283 struct i915_vma *ref[2], in compare_isolation() argument
1284 struct i915_vma *result[2], in compare_isolation() argument
1289 u32 *A[2], *B[2]; in compare_isolation()
1293 A[0] = i915_gem_object_pin_map_unlocked(ref[0]->obj, I915_MAP_WC); in compare_isolation()
1297 A[1] = i915_gem_object_pin_map_unlocked(ref[1]->obj, I915_MAP_WC); in compare_isolation()
1303 B[0] = i915_gem_object_pin_map_unlocked(result[0]->obj, I915_MAP_WC); in compare_isolation()
1309 B[1] = i915_gem_object_pin_map_unlocked(result[1]->obj, I915_MAP_WC); in compare_isolation()
1315 lrc = i915_gem_object_pin_map_unlocked(ce->state->obj, in compare_isolation()
1316 i915_coherent_map_type(engine->i915, in compare_isolation()
1317 ce->state->obj, in compare_isolation()
1325 defaults = shmem_pin_map(ce->engine->default_state); in compare_isolation()
1327 err = -ENOMEM; in compare_isolation()
1348 dw += len + 2; in compare_isolation()
1354 engine->name); in compare_isolation()
1360 len = (len + 1) / 2; in compare_isolation()
1361 while (len--) { in compare_isolation()
1371 engine->name, dw, in compare_isolation()
1375 err = -EINVAL; in compare_isolation()
1378 dw += 2; in compare_isolation()
1384 shmem_unpin_map(ce->engine->default_state, defaults); in compare_isolation()
1386 i915_gem_object_unpin_map(ce->state->obj); in compare_isolation()
1388 i915_gem_object_unpin_map(result[1]->obj); in compare_isolation()
1390 i915_gem_object_unpin_map(result[0]->obj); in compare_isolation()
1392 i915_gem_object_unpin_map(ref[1]->obj); in compare_isolation()
1394 i915_gem_object_unpin_map(ref[0]->obj); in compare_isolation()
1409 ptr = i915_gem_object_pin_map_unlocked(vma->obj, I915_MAP_WC); in create_result_vma()
1415 memset(ptr, POISON_INUSE, vma->size); in create_result_vma()
1416 i915_gem_object_flush_map(vma->obj); in create_result_vma()
1417 i915_gem_object_unpin_map(vma->obj); in create_result_vma()
1424 u32 *sema = memset32(engine->status_page.addr + 1000, 0, 1); in __lrc_isolation()
1425 struct i915_vma *ref[2], *result[2]; in __lrc_isolation()
1440 ref[0] = create_result_vma(A->vm, SZ_64K); in __lrc_isolation()
1446 ref[1] = create_result_vma(A->vm, SZ_64K); in __lrc_isolation()
1461 if (i915_request_wait(rq, 0, HZ / 2) < 0) { in __lrc_isolation()
1463 err = -ETIME; in __lrc_isolation()
1468 result[0] = create_result_vma(A->vm, SZ_64K); in __lrc_isolation()
1474 result[1] = create_result_vma(A->vm, SZ_64K); in __lrc_isolation()
1487 if (err == 0 && i915_request_wait(rq, 0, HZ / 2) < 0) { in __lrc_isolation()
1489 __func__, engine->name); in __lrc_isolation()
1490 err = -ETIME; in __lrc_isolation()
1494 WRITE_ONCE(*sema, -1); in __lrc_isolation()
1518 if (engine->class == COPY_ENGINE_CLASS && GRAPHICS_VER(engine->i915) == 9) in skip_isolation()
1521 if (engine->class == RENDER_CLASS && GRAPHICS_VER(engine->i915) == 11) in skip_isolation()
1542 * Our goal is try and verify that per-context state cannot be in live_lrc_isolation()
1543 * tampered with by another non-privileged client. in live_lrc_isolation()
1570 if (igt_flush_test(gt->i915)) { in live_lrc_isolation()
1571 err = -EIO; in live_lrc_isolation()
1592 err = -ETIME; in indirect_ctx_submit_req()
1603 emit_indirect_ctx_bb_canary(const struct intel_context *ce, u32 *cs) in emit_indirect_ctx_bb_canary() argument
1605 *cs++ = MI_STORE_REGISTER_MEM_GEN8 | in emit_indirect_ctx_bb_canary()
1608 *cs++ = i915_mmio_reg_offset(RING_START(0)); in emit_indirect_ctx_bb_canary()
1609 *cs++ = i915_ggtt_offset(ce->state) + in emit_indirect_ctx_bb_canary()
1612 *cs++ = 0; in emit_indirect_ctx_bb_canary()
1614 return cs; in emit_indirect_ctx_bb_canary()
1620 u32 *cs = context_indirect_bb(ce); in indirect_ctx_bb_setup() local
1622 cs[CTX_BB_CANARY_INDEX] = 0xdeadf00d; in indirect_ctx_bb_setup()
1624 setup_indirect_ctx_bb(ce, ce->engine, emit_indirect_ctx_bb_canary); in indirect_ctx_bb_setup()
1629 const u32 * const ctx_bb = (void *)(ce->lrc_reg_state) - in check_ring_start()
1632 if (ctx_bb[CTX_BB_CANARY_INDEX] == ce->lrc_reg_state[CTX_RING_START]) in check_ring_start()
1637 ce->lrc_reg_state[CTX_RING_START]); in check_ring_start()
1651 return -EINVAL; in indirect_ctx_bb_check()
1678 if (!a->wa_bb_page) { in __live_lrc_indirect_ctx_bb()
1679 GEM_BUG_ON(b->wa_bb_page); in __live_lrc_indirect_ctx_bb()
1680 GEM_BUG_ON(GRAPHICS_VER(engine->i915) == 12); in __live_lrc_indirect_ctx_bb()
1724 if (igt_flush_test(gt->i915)) in live_lrc_indirect_ctx_bb()
1725 err = -EIO; in live_lrc_indirect_ctx_bb()
1737 const unsigned int bit = I915_RESET_ENGINE + engine->id; in garbage_reset()
1738 unsigned long *lock = &engine->gt->reset.flags; in garbage_reset()
1742 tasklet_disable(&engine->sched_engine->tasklet); in garbage_reset()
1744 if (!rq->fence.error) in garbage_reset()
1747 tasklet_enable(&engine->sched_engine->tasklet); in garbage_reset()
1764 ce->lrc_reg_state, in garbage()
1765 ce->engine->context_size - in garbage()
1799 if (wait_for_submit(engine, hang, HZ / 2)) { in __lrc_garbage()
1801 err = -ETIME; in __lrc_garbage()
1809 if (!hang->fence.error) { in __lrc_garbage()
1812 engine->name); in __lrc_garbage()
1813 err = -EINVAL; in __lrc_garbage()
1817 if (i915_request_wait(hang, 0, HZ / 2) < 0) { in __lrc_garbage()
1819 engine->name); in __lrc_garbage()
1821 err = -EIO; in __lrc_garbage()
1849 if (!intel_has_reset_engine(engine->gt)) in live_lrc_garbage()
1860 if (igt_flush_test(gt->i915)) in live_lrc_garbage()
1861 err = -EIO; in live_lrc_garbage()
1880 ce->stats.runtime.num_underflow = 0; in __live_pphwsp_runtime()
1881 ce->stats.runtime.max_underflow = 0; in __live_pphwsp_runtime()
1893 if (--loop == 0) in __live_pphwsp_runtime()
1907 pr_err("%s: request not completed!\n", engine->name); in __live_pphwsp_runtime()
1911 igt_flush_test(engine->i915); in __live_pphwsp_runtime()
1914 engine->name, in __live_pphwsp_runtime()
1919 if (ce->stats.runtime.num_underflow) { in __live_pphwsp_runtime()
1921 engine->name, in __live_pphwsp_runtime()
1922 ce->stats.runtime.num_underflow, in __live_pphwsp_runtime()
1923 ce->stats.runtime.max_underflow); in __live_pphwsp_runtime()
1925 err = -EOVERFLOW; in __live_pphwsp_runtime()
1953 if (igt_flush_test(gt->i915)) in live_pphwsp_runtime()
1954 err = -EIO; in live_pphwsp_runtime()