Lines Matching +full:0 +full:x9680
90 unsigned int start = 0, end = wal->count; in _wa_add()
145 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == in _wa_add()
148 i915_mmio_reg_offset(wa_[0].reg)) in _wa_add()
151 swap(wa_[1], wa_[0]); in _wa_add()
178 wa_write_clr_set(wal, reg, ~0, set); in wa_write()
190 wa_write_clr_set(wal, reg, clr, 0); in wa_write_clr()
207 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); in wa_masked_en()
213 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); in wa_masked_dis()
220 wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); in wa_masked_field_set()
308 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); in bdw_ctx_workarounds_init()
423 u8 vals[3] = { 0, 0, 0 }; in skl_tune_iz_hashing()
426 for (i = 0; i < 3; i++) { in skl_tune_iz_hashing()
437 * subslice_7eu[i] != 0 (because of the check above) and in skl_tune_iz_hashing()
440 * -> 0 <= ss <= 3; in skl_tune_iz_hashing()
446 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) in skl_tune_iz_hashing()
453 GEN9_IZ_HASHING_MASK(0), in skl_tune_iz_hashing()
456 GEN9_IZ_HASHING(0, vals[0])); in skl_tune_iz_hashing()
540 wa_add(wal, GEN10_CACHE_MODE_SS, 0, in icl_ctx_workarounds_init()
542 0 /* write-only, so skip validation */, in icl_ctx_workarounds_init()
555 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); in icl_ctx_workarounds_init()
557 0, /* write-only register; skip validation */ in icl_ctx_workarounds_init()
558 0xFFFFFFFF); in icl_ctx_workarounds_init()
573 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)); in dg2_ctx_gt_tuning_init()
578 0, false); in dg2_ctx_gt_tuning_init()
605 0, false); in gen12_ctx_gt_tuning_init()
643 0, false); in gen12_ctx_workarounds_init()
692 wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); in dg2_ctx_workarounds_init()
836 if (wal->count == 0) in intel_engine_emit_ctx_wa()
837 return 0; in intel_engine_emit_ctx_wa()
848 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in intel_engine_emit_ctx_wa()
860 return 0; in intel_engine_emit_ctx_wa()
929 HSW_ROW_CHICKEN3, 0, in hsw_gt_workarounds_init()
931 0 /* XXX does this reg exist? */, true); in hsw_gt_workarounds_init()
1029 if (IS_KBL_GRAPHICS_STEP(gt->i915, 0, STEP_C0)) in kbl_gt_workarounds_init()
1108 * one of the higher subslices, we run the risk of reading back 0's or in icl_wa_init_mcr()
1111 subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0)); in icl_wa_init_mcr()
1121 __add_mcr_wa(gt, wal, 0, subslice); in icl_wa_init_mcr()
1128 unsigned long slice, subslice = 0, slice_mask = 0; in xehp_init_mcr()
1129 u32 lncf_mask = 0; in xehp_init_mcr()
1167 lncf_mask |= (0x3 << (i * 2)); in xehp_init_mcr()
1199 __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2); in xehp_init_mcr()
1200 __set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2); in xehp_init_mcr()
1213 dss = intel_sseu_find_first_xehp_dss(>->info.sseu, 0, 0); in pvc_init_mcr()
1583 enum forcewake_domains fw = 0; in wal_get_fw_for_rmw()
1587 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) in wal_get_fw_for_rmw()
1600 DRM_ERROR("%s workaround lost on %s! (reg[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x)\n", in wa_verify()
1627 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in wa_list_apply()
1628 u32 val, old = 0; in wa_list_apply()
1631 old = wa->clr ? intel_gt_mcr_read_any_fw(gt, wa->reg) : 0; in wa_list_apply()
1666 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) in wa_list_verify()
1855 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), in icl_whitelist_build()
1858 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), in icl_whitelist_build()
1861 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), in icl_whitelist_build()
1964 * Prevent read/write access to [0x4400, 0x4600) which covers in blacklist_trtt()
1969 whitelist_reg_ext(w, _MMIO(0x4400), in blacklist_trtt()
1972 whitelist_reg_ext(w, _MMIO(0x4500), in blacklist_trtt()
2035 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) in intel_engine_apply_whitelist()
2076 * Even on the few platforms where MOCS 0 is a in engine_fake_wa_init()
2081 drm_WARN_ON(&engine->i915->drm, mocs_r == 0); in engine_fake_wa_init()
2093 return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >= in needs_wa_1308578152()
2181 * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping, in rcs_engine_wa_init()
2184 wa_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, in rcs_engine_wa_init()
2186 0, false); in rcs_engine_wa_init()
2225 wa_add(wal, GEN10_CACHE_MODE_SS, 0, in rcs_engine_wa_init()
2227 0 /* Wa_14012342262 :write-only reg, so skip in rcs_engine_wa_init()
2365 0); in rcs_engine_wa_init()
2442 GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0); in rcs_engine_wa_init()
2444 GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0); in rcs_engine_wa_init()
2446 EVICTION_PERF_FIX_ENABLE, 0); in rcs_engine_wa_init()
2493 if (0) { /* causes HiZ corruption on ivb:gt1 */ in rcs_engine_wa_init()
2621 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), in rcs_engine_wa_init()
2623 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true); in rcs_engine_wa_init()
2637 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), in rcs_engine_wa_init()
2638 0 /* XXX bit doesn't stick on Broadwater */, in rcs_engine_wa_init()
2694 * Note that register 0xE420 is write-only and cannot be read in add_render_compute_tuning_settings()
2698 wa_add(wal, GEN10_CACHE_MODE_SS, 0, in add_render_compute_tuning_settings()
2700 0 /* write-only, so skip validation */, in add_render_compute_tuning_settings()
2827 { .start = 0x5500, .end = 0x55ff },
2828 { .start = 0x7000, .end = 0x7fff },
2829 { .start = 0x9400, .end = 0x97ff },
2830 { .start = 0xb000, .end = 0xb3ff },
2831 { .start = 0xe000, .end = 0xe7ff },
2836 { .start = 0x8150, .end = 0x815f },
2837 { .start = 0x9520, .end = 0x955f },
2838 { .start = 0xb100, .end = 0xb3ff },
2839 { .start = 0xde80, .end = 0xe8ff },
2840 { .start = 0x24a00, .end = 0x24a7f },
2845 { .start = 0x4000, .end = 0x4aff },
2846 { .start = 0x5200, .end = 0x52ff },
2847 { .start = 0x5400, .end = 0x7fff },
2848 { .start = 0x8140, .end = 0x815f },
2849 { .start = 0x8c80, .end = 0x8dff },
2850 { .start = 0x94d0, .end = 0x955f },
2851 { .start = 0x9680, .end = 0x96ff },
2852 { .start = 0xb000, .end = 0xb3ff },
2853 { .start = 0xc800, .end = 0xcfff },
2854 { .start = 0xd800, .end = 0xd8ff },
2855 { .start = 0xdc00, .end = 0xffff },
2856 { .start = 0x17000, .end = 0x17fff },
2857 { .start = 0x24a00, .end = 0x24a7f },
2880 for (i = 0; mcr_ranges[i].start; i++) in mcr_range()
2894 unsigned int i, count = 0; in wa_list_srm()
2902 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in wa_list_srm()
2911 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in wa_list_srm()
2920 *cs++ = 0; in wa_list_srm()
2924 return 0; in wa_list_srm()
2940 return 0; in engine_wa_list_verify()
2951 if (err == 0) in engine_wa_list_verify()
2956 err = i915_vma_pin_ww(vma, &ww, 0, 0, in engine_wa_list_verify()
2968 if (err == 0) in engine_wa_list_verify()
2970 if (err == 0) in engine_wa_list_verify()
2981 if (i915_request_wait(rq, 0, HZ / 5) < 0) { in engine_wa_list_verify()
2992 err = 0; in engine_wa_list_verify()
2993 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in engine_wa_list_verify()