273 	 * Although gen12 architecture supported multiple slices, TGL, RKL,  in gen12_sseu_info_init()
310 	 * Although gen11 architecture supported multiple slices, ICL and  in gen11_sseu_info_init()
400 	 * to each of the enabled slices.  in gen9_sseu_info_init()
407 	 * Iterate through enabled slices and subslices to  in gen9_sseu_info_init()
502 	 * to each of the enabled slices.  in bdw_sseu_info_init()
519 	 * Iterate through enabled slices and subslices to  in bdw_sseu_info_init()
582 	 * There isn't a register to tell us how many slices/subslices. We  in hsw_sseu_info_init()
666 	u8 slices, subslices;  in intel_sseu_make_rpcs()  local
683 	slices = hweight8(req_sseu->slice_mask);  in intel_sseu_make_rpcs()
698 	 * If enabled subslice count is greater than four, two whole slices must  in intel_sseu_make_rpcs()
712 	    slices == 1 &&  in intel_sseu_make_rpcs()
717 		slices *= 2;  in intel_sseu_make_rpcs()
727 		u32 mask, val = slices;  in intel_sseu_make_rpcs()