33 static void set_hwstam(struct intel_engine_cs *engine, u32 mask)  in set_hwstam()  argument
39 	if (engine->class == RENDER_CLASS) {  in set_hwstam()
40 		if (GRAPHICS_VER(engine->i915) >= 6)  in set_hwstam()
46 	intel_engine_set_hwsp_writemask(engine, mask);  in set_hwstam()
49 static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys)  in set_hws_pga()  argument
54 	if (GRAPHICS_VER(engine->i915) >= 4)  in set_hws_pga()
57 	intel_uncore_write(engine->uncore, HWS_PGA, addr);  in set_hws_pga()
60 static struct page *status_page(struct intel_engine_cs *engine)  in status_page()  argument
62 	struct drm_i915_gem_object *obj = engine->status_page.vma->obj;  in status_page()
68 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)  in ring_setup_phys_status_page()  argument
70 	set_hws_pga(engine, PFN_PHYS(page_to_pfn(status_page(engine))));  in ring_setup_phys_status_page()
71 	set_hwstam(engine, ~0u);  in ring_setup_phys_status_page()
74 static void set_hwsp(struct intel_engine_cs *engine, u32 offset)  in set_hwsp()  argument
82 	if (GRAPHICS_VER(engine->i915) == 7) {  in set_hwsp()
83 		switch (engine->id) {  in set_hwsp()
89 			GEM_BUG_ON(engine->id);  in set_hwsp()
104 	} else if (GRAPHICS_VER(engine->i915) == 6) {  in set_hwsp()
105 		hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);  in set_hwsp()
107 		hwsp = RING_HWS_PGA(engine->mmio_base);  in set_hwsp()
110 	intel_uncore_write_fw(engine->uncore, hwsp, offset);  in set_hwsp()
111 	intel_uncore_posting_read_fw(engine->uncore, hwsp);  in set_hwsp()
114 static void flush_cs_tlb(struct intel_engine_cs *engine)  in flush_cs_tlb()  argument
116 	if (!IS_GRAPHICS_VER(engine->i915, 6, 7))  in flush_cs_tlb()
120 	if ((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0)  in flush_cs_tlb()
121 		drm_warn(&engine->i915->drm, "%s not idle before sync flush!\n",  in flush_cs_tlb()
122 			 engine->name);  in flush_cs_tlb()
124 	ENGINE_WRITE_FW(engine, RING_INSTPM,  in flush_cs_tlb()
127 	if (__intel_wait_for_register_fw(engine->uncore,  in flush_cs_tlb()
128 					 RING_INSTPM(engine->mmio_base),  in flush_cs_tlb()
131 		ENGINE_TRACE(engine,  in flush_cs_tlb()
135 static void ring_setup_status_page(struct intel_engine_cs *engine)  in ring_setup_status_page()  argument
137 	set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma));  in ring_setup_status_page()
138 	set_hwstam(engine, ~0u);  in ring_setup_status_page()
140 	flush_cs_tlb(engine);  in ring_setup_status_page()
156 static void set_pp_dir(struct intel_engine_cs *engine)  in set_pp_dir()  argument
158 	struct i915_address_space *vm = vm_alias(engine->gt->vm);  in set_pp_dir()
163 	ENGINE_WRITE_FW(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);  in set_pp_dir()
164 	ENGINE_WRITE_FW(engine, RING_PP_DIR_BASE, pp_dir(vm));  in set_pp_dir()
166 	if (GRAPHICS_VER(engine->i915) >= 7) {  in set_pp_dir()
167 		ENGINE_WRITE_FW(engine,  in set_pp_dir()
173 static bool stop_ring(struct intel_engine_cs *engine)  in stop_ring()  argument
176 	ENGINE_WRITE_FW(engine, RING_HEAD, ENGINE_READ_FW(engine, RING_TAIL));  in stop_ring()
177 	ENGINE_POSTING_READ(engine, RING_HEAD);  in stop_ring()
180 	ENGINE_WRITE_FW(engine, RING_CTL, 0);  in stop_ring()
181 	ENGINE_POSTING_READ(engine, RING_CTL);  in stop_ring()
184 	ENGINE_WRITE_FW(engine, RING_HEAD, 0);  in stop_ring()
185 	ENGINE_WRITE_FW(engine, RING_TAIL, 0);  in stop_ring()
187 	return (ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) == 0;  in stop_ring()
190 static int xcs_resume(struct intel_engine_cs *engine)  in xcs_resume()  argument
192 	struct intel_ring *ring = engine->legacy.ring;  in xcs_resume()
194 	ENGINE_TRACE(engine, "ring:{HEAD:%04x, TAIL:%04x}\n",  in xcs_resume()
201 	intel_synchronize_hardirq(engine->i915);  in xcs_resume()
202 	if (!stop_ring(engine))  in xcs_resume()
205 	if (HWS_NEEDS_PHYSICAL(engine->i915))  in xcs_resume()
206 		ring_setup_phys_status_page(engine);  in xcs_resume()
208 		ring_setup_status_page(engine);  in xcs_resume()
210 	intel_breadcrumbs_reset(engine->breadcrumbs);  in xcs_resume()
213 	ENGINE_POSTING_READ(engine, RING_HEAD);  in xcs_resume()
221 	ENGINE_WRITE_FW(engine, RING_START, i915_ggtt_offset(ring->vma));  in xcs_resume()
228 	set_pp_dir(engine);  in xcs_resume()
231 	ENGINE_WRITE_FW(engine, RING_HEAD, ring->head);  in xcs_resume()
232 	ENGINE_WRITE_FW(engine, RING_TAIL, ring->head);  in xcs_resume()
233 	ENGINE_POSTING_READ(engine, RING_TAIL);  in xcs_resume()
235 	ENGINE_WRITE_FW(engine, RING_CTL,  in xcs_resume()
239 	if (__intel_wait_for_register_fw(engine->uncore,  in xcs_resume()
240 					 RING_CTL(engine->mmio_base),  in xcs_resume()
245 	if (GRAPHICS_VER(engine->i915) > 2)  in xcs_resume()
246 		ENGINE_WRITE_FW(engine,  in xcs_resume()
251 		ENGINE_WRITE_FW(engine, RING_TAIL, ring->tail);  in xcs_resume()
252 		ENGINE_POSTING_READ(engine, RING_TAIL);  in xcs_resume()
256 	intel_engine_signal_breadcrumbs(engine);  in xcs_resume()
260 	drm_err(&engine->i915->drm,  in xcs_resume()
263 		engine->name,  in xcs_resume()
264 		ENGINE_READ(engine, RING_CTL),  in xcs_resume()
265 		ENGINE_READ(engine, RING_CTL) & RING_VALID,  in xcs_resume()
266 		ENGINE_READ(engine, RING_HEAD), ring->head,  in xcs_resume()
267 		ENGINE_READ(engine, RING_TAIL), ring->tail,  in xcs_resume()
268 		ENGINE_READ(engine, RING_START),  in xcs_resume()
273 static void sanitize_hwsp(struct intel_engine_cs *engine)  in sanitize_hwsp()  argument
277 	list_for_each_entry(tl, &engine->status_page.timelines, engine_link)  in sanitize_hwsp()
281 static void xcs_sanitize(struct intel_engine_cs *engine)  in xcs_sanitize()  argument
293 		memset(engine->status_page.addr, POISON_INUSE, PAGE_SIZE);  in xcs_sanitize()
300 	sanitize_hwsp(engine);  in xcs_sanitize()
303 	drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);  in xcs_sanitize()
305 	intel_engine_reset_pinned_contexts(engine);  in xcs_sanitize()
308 static void reset_prepare(struct intel_engine_cs *engine)  in reset_prepare()  argument
325 	ENGINE_TRACE(engine, "\n");  in reset_prepare()
326 	intel_engine_stop_cs(engine);  in reset_prepare()
328 	if (!stop_ring(engine)) {  in reset_prepare()
330 		ENGINE_TRACE(engine,  in reset_prepare()
333 			     ENGINE_READ_FW(engine, RING_CTL),  in reset_prepare()
334 			     ENGINE_READ_FW(engine, RING_HEAD),  in reset_prepare()
335 			     ENGINE_READ_FW(engine, RING_TAIL),  in reset_prepare()
336 			     ENGINE_READ_FW(engine, RING_START));  in reset_prepare()
337 		if (!stop_ring(engine)) {  in reset_prepare()
338 			drm_err(&engine->i915->drm,  in reset_prepare()
341 				engine->name,  in reset_prepare()
342 				ENGINE_READ_FW(engine, RING_CTL),  in reset_prepare()
343 				ENGINE_READ_FW(engine, RING_HEAD),  in reset_prepare()
344 				ENGINE_READ_FW(engine, RING_TAIL),  in reset_prepare()
345 				ENGINE_READ_FW(engine, RING_START));  in reset_prepare()
350 static void reset_rewind(struct intel_engine_cs *engine, bool stalled)  in reset_rewind()  argument
357 	spin_lock_irqsave(&engine->sched_engine->lock, flags);  in reset_rewind()
359 	list_for_each_entry(pos, &engine->sched_engine->requests, sched.link) {  in reset_rewind()
368 	 * The guilty request will get skipped on a hung engine.  in reset_rewind()
407 		GEM_BUG_ON(rq->ring != engine->legacy.ring);  in reset_rewind()
410 		head = engine->legacy.ring->tail;  in reset_rewind()
412 	engine->legacy.ring->head = intel_ring_wrap(engine->legacy.ring, head);  in reset_rewind()
414 	spin_unlock_irqrestore(&engine->sched_engine->lock, flags);  in reset_rewind()
417 static void reset_finish(struct intel_engine_cs *engine)  in reset_finish()  argument
421 static void reset_cancel(struct intel_engine_cs *engine)  in reset_cancel()  argument
426 	spin_lock_irqsave(&engine->sched_engine->lock, flags);  in reset_cancel()
429 	list_for_each_entry(request, &engine->sched_engine->requests, sched.link)  in reset_cancel()
431 	intel_engine_signal_breadcrumbs(engine);  in reset_cancel()
435 	spin_unlock_irqrestore(&engine->sched_engine->lock, flags);  in reset_cancel()
443 	ENGINE_WRITE(request->engine, RING_TAIL,  in i9xx_submit_request()
475 	shmem_read(ce->engine->default_state, 0,  in ring_context_init_default_state()
476 		   vaddr, ce->engine->context_size);  in ring_context_init_default_state()
492 	if (ce->engine->default_state &&  in ring_context_pre_pin()
525 alloc_context_vma(struct intel_engine_cs *engine)  in alloc_context_vma()  argument
527 	struct drm_i915_private *i915 = engine->i915;  in alloc_context_vma()
532 	obj = i915_gem_object_create_shmem(i915, engine->context_size);  in alloc_context_vma()
554 	vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);  in alloc_context_vma()
569 	struct intel_engine_cs *engine = ce->engine;  in ring_context_alloc()  local
572 	GEM_BUG_ON(!engine->legacy.ring);  in ring_context_alloc()
573 	ce->ring = engine->legacy.ring;  in ring_context_alloc()
574 	ce->timeline = intel_timeline_get(engine->legacy.timeline);  in ring_context_alloc()
577 	if (engine->context_size) {  in ring_context_alloc()
580 		vma = alloc_context_vma(engine);  in ring_context_alloc()
605 	struct intel_engine_cs *engine;  in ring_context_revoke()  local
610 	engine = rq->engine;  in ring_context_revoke()
611 	lockdep_assert_held(&engine->sched_engine->lock);  in ring_context_revoke()
612 	list_for_each_entry_continue(rq, &engine->sched_engine->requests,  in ring_context_revoke()
623 	struct intel_engine_cs *engine = NULL;  in ring_context_cancel_request()  local
625 	i915_request_active_engine(rq, &engine);  in ring_context_cancel_request()
627 	if (engine && intel_engine_pulse(engine))  in ring_context_cancel_request()
628 		intel_gt_handle_error(engine->gt, engine->mask, 0,  in ring_context_cancel_request()
656 	const struct intel_engine_cs * const engine = rq->engine;  in load_pd_dir()  local
664 	*cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));  in load_pd_dir()
668 	*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));  in load_pd_dir()
673 	*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));  in load_pd_dir()
674 	*cs++ = intel_gt_scratch_offset(engine->gt,  in load_pd_dir()
678 	*cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base));  in load_pd_dir()
683 	return rq->engine->emit_flush(rq, EMIT_FLUSH);  in load_pd_dir()
690 	struct intel_engine_cs *engine = rq->engine;  in mi_set_context()  local
691 	struct drm_i915_private *i915 = engine->i915;  in mi_set_context()
694 		IS_HASWELL(i915) ? engine->gt->info.num_engines - 1 : 0;  in mi_set_context()
722 			for_each_engine(signaller, engine->gt, id) {  in mi_set_context()
723 				if (signaller == engine)  in mi_set_context()
756 		*cs++ = i915_ggtt_offset(engine->kernel_context->state) |  in mi_set_context()
776 			for_each_engine(signaller, engine->gt, id) {  in mi_set_context()
777 				if (signaller == engine)  in mi_set_context()
789 			*cs++ = intel_gt_scratch_offset(engine->gt,  in mi_set_context()
806 	u32 *cs, *remap_info = rq->engine->i915->l3_parity.remap_info[slice];  in remap_l3_slice()
861 	ret = rq->engine->emit_flush(rq, EMIT_FLUSH);  in switch_mm()
877 	return rq->engine->emit_flush(rq, EMIT_INVALIDATE);  in switch_mm()
882 	struct intel_engine_cs *engine = rq->engine;  in clear_residuals()  local
885 	ret = switch_mm(rq, vm_alias(engine->kernel_context->vm));  in clear_residuals()
889 	if (engine->kernel_context->state) {  in clear_residuals()
891 				     engine->kernel_context,  in clear_residuals()
897 	ret = engine->emit_bb_start(rq,  in clear_residuals()
898 				    engine->wa_ctx.vma->node.start, 0,  in clear_residuals()
903 	ret = engine->emit_flush(rq, EMIT_FLUSH);  in clear_residuals()
908 	return engine->emit_flush(rq, EMIT_INVALIDATE);  in clear_residuals()
913 	struct intel_engine_cs *engine = rq->engine;  in switch_context()  local
918 	GEM_BUG_ON(HAS_EXECLISTS(engine->i915));  in switch_context()
920 	if (engine->wa_ctx.vma && ce != engine->kernel_context) {  in switch_context()
921 		if (engine->wa_ctx.vma->private != ce &&  in switch_context()
927 			residuals = &engine->wa_ctx.vma->private;  in switch_context()
938 		GEM_BUG_ON(engine->id != RCS0);  in switch_context()
991 	ret = request->engine->emit_flush(request, EMIT_INVALIDATE);  in ring_request_alloc()
1005 	struct intel_uncore *uncore = request->engine->uncore;  in gen6_bsd_submit_request()
1041 static void i9xx_set_default_submission(struct intel_engine_cs *engine)  in i9xx_set_default_submission()  argument
1043 	engine->submit_request = i9xx_submit_request;  in i9xx_set_default_submission()
1046 static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)  in gen6_bsd_set_default_submission()  argument
1048 	engine->submit_request = gen6_bsd_submit_request;  in gen6_bsd_set_default_submission()
1051 static void ring_release(struct intel_engine_cs *engine)  in ring_release()  argument
1053 	struct drm_i915_private *dev_priv = engine->i915;  in ring_release()
1056 		    (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);  in ring_release()
1058 	intel_engine_cleanup_common(engine);  in ring_release()
1060 	if (engine->wa_ctx.vma) {  in ring_release()
1061 		intel_context_put(engine->wa_ctx.vma->private);  in ring_release()
1062 		i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0);  in ring_release()
1065 	intel_ring_unpin(engine->legacy.ring);  in ring_release()
1066 	intel_ring_put(engine->legacy.ring);  in ring_release()
1068 	intel_timeline_unpin(engine->legacy.timeline);  in ring_release()
1069 	intel_timeline_put(engine->legacy.timeline);  in ring_release()
1072 static void irq_handler(struct intel_engine_cs *engine, u16 iir)  in irq_handler()  argument
1074 	intel_engine_signal_breadcrumbs(engine);  in irq_handler()
1077 static void setup_irq(struct intel_engine_cs *engine)  in setup_irq()  argument
1079 	struct drm_i915_private *i915 = engine->i915;  in setup_irq()
1081 	intel_engine_set_irq_handler(engine, irq_handler);  in setup_irq()
1084 		engine->irq_enable = gen6_irq_enable;  in setup_irq()
1085 		engine->irq_disable = gen6_irq_disable;  in setup_irq()
1087 		engine->irq_enable = gen5_irq_enable;  in setup_irq()
1088 		engine->irq_disable = gen5_irq_disable;  in setup_irq()
1090 		engine->irq_enable = gen3_irq_enable;  in setup_irq()
1091 		engine->irq_disable = gen3_irq_disable;  in setup_irq()
1093 		engine->irq_enable = gen2_irq_enable;  in setup_irq()
1094 		engine->irq_disable = gen2_irq_disable;  in setup_irq()
1100 	lockdep_assert_held(&rq->engine->sched_engine->lock);  in add_to_engine()
1101 	list_move_tail(&rq->sched.link, &rq->engine->sched_engine->requests);  in add_to_engine()
1106 	spin_lock_irq(&rq->engine->sched_engine->lock);  in remove_from_engine()
1112 	spin_unlock_irq(&rq->engine->sched_engine->lock);  in remove_from_engine()
1117 static void setup_common(struct intel_engine_cs *engine)  in setup_common()  argument
1119 	struct drm_i915_private *i915 = engine->i915;  in setup_common()
1124 	setup_irq(engine);  in setup_common()
1126 	engine->resume = xcs_resume;  in setup_common()
1127 	engine->sanitize = xcs_sanitize;  in setup_common()
1129 	engine->reset.prepare = reset_prepare;  in setup_common()
1130 	engine->reset.rewind = reset_rewind;  in setup_common()
1131 	engine->reset.cancel = reset_cancel;  in setup_common()
1132 	engine->reset.finish = reset_finish;  in setup_common()
1134 	engine->add_active_request = add_to_engine;  in setup_common()
1135 	engine->remove_active_request = remove_from_engine;  in setup_common()
1137 	engine->cops = &ring_context_ops;  in setup_common()
1138 	engine->request_alloc = ring_request_alloc;  in setup_common()
1143 	 * engine->emit_init_breadcrumb().  in setup_common()
1145 	engine->emit_fini_breadcrumb = gen3_emit_breadcrumb;  in setup_common()
1147 		engine->emit_fini_breadcrumb = gen5_emit_breadcrumb;  in setup_common()
1149 	engine->set_default_submission = i9xx_set_default_submission;  in setup_common()
1152 		engine->emit_bb_start = gen6_emit_bb_start;  in setup_common()
1154 		engine->emit_bb_start = gen4_emit_bb_start;  in setup_common()
1156 		engine->emit_bb_start = i830_emit_bb_start;  in setup_common()
1158 		engine->emit_bb_start = gen3_emit_bb_start;  in setup_common()
1161 static void setup_rcs(struct intel_engine_cs *engine)  in setup_rcs()  argument
1163 	struct drm_i915_private *i915 = engine->i915;  in setup_rcs()
1166 		engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;  in setup_rcs()
1168 	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;  in setup_rcs()
1171 		engine->emit_flush = gen7_emit_flush_rcs;  in setup_rcs()
1172 		engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs;  in setup_rcs()
1174 		engine->emit_flush = gen6_emit_flush_rcs;  in setup_rcs()
1175 		engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs;  in setup_rcs()
1177 		engine->emit_flush = gen4_emit_flush_rcs;  in setup_rcs()
1180 			engine->emit_flush = gen2_emit_flush;  in setup_rcs()
1182 			engine->emit_flush = gen4_emit_flush_rcs;  in setup_rcs()
1183 		engine->irq_enable_mask = I915_USER_INTERRUPT;  in setup_rcs()
1187 		engine->emit_bb_start = hsw_emit_bb_start;  in setup_rcs()
1190 static void setup_vcs(struct intel_engine_cs *engine)  in setup_vcs()  argument
1192 	struct drm_i915_private *i915 = engine->i915;  in setup_vcs()
1197 			engine->set_default_submission = gen6_bsd_set_default_submission;  in setup_vcs()
1198 		engine->emit_flush = gen6_emit_flush_vcs;  in setup_vcs()
1199 		engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;  in setup_vcs()
1202 			engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;  in setup_vcs()
1204 			engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;  in setup_vcs()
1206 		engine->emit_flush = gen4_emit_flush_vcs;  in setup_vcs()
1208 			engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;  in setup_vcs()
1210 			engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;  in setup_vcs()
1214 static void setup_bcs(struct intel_engine_cs *engine)  in setup_bcs()  argument
1216 	struct drm_i915_private *i915 = engine->i915;  in setup_bcs()
1218 	engine->emit_flush = gen6_emit_flush_xcs;  in setup_bcs()
1219 	engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;  in setup_bcs()
1222 		engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;  in setup_bcs()
1224 		engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;  in setup_bcs()
1227 static void setup_vecs(struct intel_engine_cs *engine)  in setup_vecs()  argument
1229 	struct drm_i915_private *i915 = engine->i915;  in setup_vecs()
1233 	engine->emit_flush = gen6_emit_flush_xcs;  in setup_vecs()
1234 	engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;  in setup_vecs()
1235 	engine->irq_enable = hsw_irq_enable_vecs;  in setup_vecs()
1236 	engine->irq_disable = hsw_irq_disable_vecs;  in setup_vecs()
1238 	engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;  in setup_vecs()
1241 static int gen7_ctx_switch_bb_setup(struct intel_engine_cs * const engine,  in gen7_ctx_switch_bb_setup()  argument
1244 	return gen7_setup_clear_gpr_bb(engine, vma);  in gen7_ctx_switch_bb_setup()
1247 static int gen7_ctx_switch_bb_init(struct intel_engine_cs *engine,  in gen7_ctx_switch_bb_init()  argument
1261 	err = gen7_ctx_switch_bb_setup(engine, vma);  in gen7_ctx_switch_bb_init()
1265 	engine->wa_ctx.vma = vma;  in gen7_ctx_switch_bb_init()
1273 static struct i915_vma *gen7_ctx_vma(struct intel_engine_cs *engine)  in gen7_ctx_vma()  argument
1279 	if (GRAPHICS_VER(engine->i915) != 7 || engine->class != RENDER_CLASS)  in gen7_ctx_vma()
1282 	err = gen7_ctx_switch_bb_setup(engine, NULL /* probe size */);  in gen7_ctx_vma()
1290 	obj = i915_gem_object_create_internal(engine->i915, size);  in gen7_ctx_vma()
1294 	vma = i915_vma_instance(obj, engine->gt->vm, NULL);  in gen7_ctx_vma()
1300 	vma->private = intel_context_create(engine); /* dummy residuals */  in gen7_ctx_vma()
1311 int intel_ring_submission_setup(struct intel_engine_cs *engine)  in intel_ring_submission_setup()  argument
1319 	setup_common(engine);  in intel_ring_submission_setup()
1321 	switch (engine->class) {  in intel_ring_submission_setup()
1323 		setup_rcs(engine);  in intel_ring_submission_setup()
1326 		setup_vcs(engine);  in intel_ring_submission_setup()
1329 		setup_bcs(engine);  in intel_ring_submission_setup()
1332 		setup_vecs(engine);  in intel_ring_submission_setup()
1335 		MISSING_CASE(engine->class);  in intel_ring_submission_setup()
1339 	timeline = intel_timeline_create_from_engine(engine,  in intel_ring_submission_setup()
1347 	ring = intel_engine_create_ring(engine, SZ_16K);  in intel_ring_submission_setup()
1353 	GEM_BUG_ON(engine->legacy.ring);  in intel_ring_submission_setup()
1354 	engine->legacy.ring = ring;  in intel_ring_submission_setup()
1355 	engine->legacy.timeline = timeline;  in intel_ring_submission_setup()
1357 	gen7_wa_vma = gen7_ctx_vma(engine);  in intel_ring_submission_setup()
1370 		err = i915_gem_object_lock(engine->legacy.ring->vma->obj, &ww);  in intel_ring_submission_setup()
1381 	GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma);  in intel_ring_submission_setup()
1384 		err = gen7_ctx_switch_bb_init(engine, &ww, gen7_wa_vma);  in intel_ring_submission_setup()
1402 	engine->release = ring_release;  in intel_ring_submission_setup()
1416 	intel_engine_cleanup_common(engine);  in intel_ring_submission_setup()