Lines Matching full:llc
53 /* (e)LLC caching options */
134 * Thus it is expected to allow LLC cacheability to enable coherent
154 /* Base - L3 + LLC */ \
166 /* Base - LLC */ \
170 /* Age 0 - LLC */ \
174 /* Age 0 - L3 + LLC */ \
178 /* Age: Don't Chg. - LLC */ \
182 /* Age: Don't Chg. - L3 + LLC */ \
186 /* No AOM - LLC */ \
190 /* No AOM - L3 + LLC */ \
194 /* No AOM; Age 0 - LLC */ \
198 /* No AOM; Age 0 - L3 + LLC */ \
202 /* No AOM; Age:DC - LLC */ \
206 /* No AOM; Age:DC - L3 + LLC */ \
210 /* Bypass LLC - Uncached (EHL+) */ \
214 /* Bypass LLC - L3 (Read-Only) (EHL+) */ \
218 /* Self-Snoop - L3 + LLC */ \
222 /* Skip Caching - L3 + LLC(12.5%) */ \
226 /* Skip Caching - L3 + LLC(25%) */ \
230 /* Skip Caching - L3 + LLC(50%) */ \
234 /* Skip Caching - L3 + LLC(75%) */ \
238 /* Skip Caching - L3 + LLC(87.5%) */ \
266 /* Implicitly enable L1 - HDC:L1 + L3 + LLC */
274 /* Implicitly enable L1 - HDC:L1 + LLC */
332 /* Implicitly enable L1 - HDC:L1 + L3 + LLC */
340 /* Implicitly enable L1 - HDC:L1 + LLC */
663 * LLC and eDRAM control values are not applicable to dgfx in intel_mocs_init()