Lines Matching +full:0 +full:x168
29 #define POSTED BIT(0) in set_offsets()
30 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) in set_offsets()
32 (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \ in set_offsets()
33 (((x) >> 2) & 0x7f) in set_offsets()
34 #define END 0 in set_offsets()
47 count = *data & 0x3f; in set_offsets()
60 u32 offset = 0; in set_offsets()
69 regs[0] = base + (offset << 2); in set_offsets()
78 *regs |= BIT(0); in set_offsets()
84 LRI(11, 0),
85 REG16(0x244),
86 REG(0x034),
87 REG(0x030),
88 REG(0x038),
89 REG(0x03c),
90 REG(0x168),
91 REG(0x140),
92 REG(0x110),
93 REG(0x11c),
94 REG(0x114),
95 REG(0x118),
98 LRI(9, 0),
99 REG16(0x3a8),
100 REG16(0x28c),
101 REG16(0x288),
102 REG16(0x284),
103 REG16(0x280),
104 REG16(0x27c),
105 REG16(0x278),
106 REG16(0x274),
107 REG16(0x270),
110 LRI(2, 0),
111 REG16(0x200),
112 REG(0x028),
120 REG16(0x244),
121 REG(0x034),
122 REG(0x030),
123 REG(0x038),
124 REG(0x03c),
125 REG(0x168),
126 REG(0x140),
127 REG(0x110),
128 REG(0x11c),
129 REG(0x114),
130 REG(0x118),
131 REG(0x1c0),
132 REG(0x1c4),
133 REG(0x1c8),
137 REG16(0x3a8),
138 REG16(0x28c),
139 REG16(0x288),
140 REG16(0x284),
141 REG16(0x280),
142 REG16(0x27c),
143 REG16(0x278),
144 REG16(0x274),
145 REG16(0x270),
149 REG16(0x200),
153 REG(0x028),
154 REG(0x09c),
155 REG(0x0c0),
156 REG(0x178),
157 REG(0x17c),
158 REG16(0x358),
159 REG(0x170),
160 REG(0x150),
161 REG(0x154),
162 REG(0x158),
163 REG16(0x41c),
164 REG16(0x600),
165 REG16(0x604),
166 REG16(0x608),
167 REG16(0x60c),
168 REG16(0x610),
169 REG16(0x614),
170 REG16(0x618),
171 REG16(0x61c),
172 REG16(0x620),
173 REG16(0x624),
174 REG16(0x628),
175 REG16(0x62c),
176 REG16(0x630),
177 REG16(0x634),
178 REG16(0x638),
179 REG16(0x63c),
180 REG16(0x640),
181 REG16(0x644),
182 REG16(0x648),
183 REG16(0x64c),
184 REG16(0x650),
185 REG16(0x654),
186 REG16(0x658),
187 REG16(0x65c),
188 REG16(0x660),
189 REG16(0x664),
190 REG16(0x668),
191 REG16(0x66c),
192 REG16(0x670),
193 REG16(0x674),
194 REG16(0x678),
195 REG16(0x67c),
196 REG(0x068),
204 REG16(0x244),
205 REG(0x034),
206 REG(0x030),
207 REG(0x038),
208 REG(0x03c),
209 REG(0x168),
210 REG(0x140),
211 REG(0x110),
212 REG(0x1c0),
213 REG(0x1c4),
214 REG(0x1c8),
215 REG(0x180),
216 REG16(0x2b4),
220 REG16(0x3a8),
221 REG16(0x28c),
222 REG16(0x288),
223 REG16(0x284),
224 REG16(0x280),
225 REG16(0x27c),
226 REG16(0x278),
227 REG16(0x274),
228 REG16(0x270),
236 REG16(0x244),
237 REG(0x034),
238 REG(0x030),
239 REG(0x038),
240 REG(0x03c),
241 REG(0x168),
242 REG(0x140),
243 REG(0x110),
244 REG(0x1c0),
245 REG(0x1c4),
246 REG(0x1c8),
247 REG(0x180),
248 REG16(0x2b4),
249 REG(0x120),
250 REG(0x124),
254 REG16(0x3a8),
255 REG16(0x28c),
256 REG16(0x288),
257 REG16(0x284),
258 REG16(0x280),
259 REG16(0x27c),
260 REG16(0x278),
261 REG16(0x274),
262 REG16(0x270),
270 REG16(0x244),
271 REG(0x034),
272 REG(0x030),
273 REG(0x038),
274 REG(0x03c),
275 REG(0x168),
276 REG(0x140),
277 REG(0x110),
278 REG(0x11c),
279 REG(0x114),
280 REG(0x118),
281 REG(0x1c0),
282 REG(0x1c4),
283 REG(0x1c8),
287 REG16(0x3a8),
288 REG16(0x28c),
289 REG16(0x288),
290 REG16(0x284),
291 REG16(0x280),
292 REG16(0x27c),
293 REG16(0x278),
294 REG16(0x274),
295 REG16(0x270),
298 LRI(1, 0),
299 REG(0x0c8),
307 REG16(0x244),
308 REG(0x34),
309 REG(0x30),
310 REG(0x38),
311 REG(0x3c),
312 REG(0x168),
313 REG(0x140),
314 REG(0x110),
315 REG(0x11c),
316 REG(0x114),
317 REG(0x118),
318 REG(0x1c0),
319 REG(0x1c4),
320 REG(0x1c8),
324 REG16(0x3a8),
325 REG16(0x28c),
326 REG16(0x288),
327 REG16(0x284),
328 REG16(0x280),
329 REG16(0x27c),
330 REG16(0x278),
331 REG16(0x274),
332 REG16(0x270),
335 LRI(1, 0),
336 REG(0xc8),
340 REG(0x28),
341 REG(0x9c),
342 REG(0xc0),
343 REG(0x178),
344 REG(0x17c),
345 REG16(0x358),
346 REG(0x170),
347 REG(0x150),
348 REG(0x154),
349 REG(0x158),
350 REG16(0x41c),
351 REG16(0x600),
352 REG16(0x604),
353 REG16(0x608),
354 REG16(0x60c),
355 REG16(0x610),
356 REG16(0x614),
357 REG16(0x618),
358 REG16(0x61c),
359 REG16(0x620),
360 REG16(0x624),
361 REG16(0x628),
362 REG16(0x62c),
363 REG16(0x630),
364 REG16(0x634),
365 REG16(0x638),
366 REG16(0x63c),
367 REG16(0x640),
368 REG16(0x644),
369 REG16(0x648),
370 REG16(0x64c),
371 REG16(0x650),
372 REG16(0x654),
373 REG16(0x658),
374 REG16(0x65c),
375 REG16(0x660),
376 REG16(0x664),
377 REG16(0x668),
378 REG16(0x66c),
379 REG16(0x670),
380 REG16(0x674),
381 REG16(0x678),
382 REG16(0x67c),
383 REG(0x68),
391 REG16(0x244),
392 REG(0x034),
393 REG(0x030),
394 REG(0x038),
395 REG(0x03c),
396 REG(0x168),
397 REG(0x140),
398 REG(0x110),
399 REG(0x11c),
400 REG(0x114),
401 REG(0x118),
402 REG(0x1c0),
403 REG(0x1c4),
404 REG(0x1c8),
405 REG(0x180),
409 REG16(0x3a8),
410 REG16(0x28c),
411 REG16(0x288),
412 REG16(0x284),
413 REG16(0x280),
414 REG16(0x27c),
415 REG16(0x278),
416 REG16(0x274),
417 REG16(0x270),
420 REG(0x1b0),
423 LRI(1, 0),
424 REG(0x0c8),
432 REG16(0x244),
433 REG(0x034),
434 REG(0x030),
435 REG(0x038),
436 REG(0x03c),
437 REG(0x168),
438 REG(0x140),
439 REG(0x110),
440 REG(0x1c0),
441 REG(0x1c4),
442 REG(0x1c8),
443 REG(0x180),
444 REG16(0x2b4),
448 REG16(0x3a8),
449 REG16(0x28c),
450 REG16(0x288),
451 REG16(0x284),
452 REG16(0x280),
453 REG16(0x27c),
454 REG16(0x278),
455 REG16(0x274),
456 REG16(0x270),
459 REG(0x1b0),
460 REG16(0x5a8),
461 REG16(0x5ac),
464 LRI(1, 0),
465 REG(0x0c8),
469 REG16(0x588),
470 REG16(0x588),
471 REG16(0x588),
472 REG16(0x588),
473 REG16(0x588),
474 REG16(0x588),
475 REG(0x028),
476 REG(0x09c),
477 REG(0x0c0),
478 REG(0x178),
479 REG(0x17c),
480 REG16(0x358),
481 REG(0x170),
482 REG(0x150),
483 REG(0x154),
484 REG(0x158),
485 REG16(0x41c),
486 REG16(0x600),
487 REG16(0x604),
488 REG16(0x608),
489 REG16(0x60c),
490 REG16(0x610),
491 REG16(0x614),
492 REG16(0x618),
493 REG16(0x61c),
494 REG16(0x620),
495 REG16(0x624),
496 REG16(0x628),
497 REG16(0x62c),
498 REG16(0x630),
499 REG16(0x634),
500 REG16(0x638),
501 REG16(0x63c),
502 REG16(0x640),
503 REG16(0x644),
504 REG16(0x648),
505 REG16(0x64c),
506 REG16(0x650),
507 REG16(0x654),
508 REG16(0x658),
509 REG16(0x65c),
510 REG16(0x660),
511 REG16(0x664),
512 REG16(0x668),
513 REG16(0x66c),
514 REG16(0x670),
515 REG16(0x674),
516 REG16(0x678),
517 REG16(0x67c),
518 REG(0x068),
519 REG(0x084),
528 REG16(0x244),
529 REG(0x034),
530 REG(0x030),
531 REG(0x038),
532 REG(0x03c),
533 REG(0x168),
534 REG(0x140),
535 REG(0x110),
536 REG(0x1c0),
537 REG(0x1c4),
538 REG(0x1c8),
539 REG(0x180),
540 REG16(0x2b4),
544 REG16(0x3a8),
545 REG16(0x28c),
546 REG16(0x288),
547 REG16(0x284),
548 REG16(0x280),
549 REG16(0x27c),
550 REG16(0x278),
551 REG16(0x274),
552 REG16(0x270),
555 REG(0x1b0),
556 REG16(0x5a8),
557 REG16(0x5ac),
560 LRI(1, 0),
561 REG(0x0c8),
569 REG16(0x244),
570 REG(0x034),
571 REG(0x030),
572 REG(0x038),
573 REG(0x03c),
574 REG(0x168),
575 REG(0x140),
576 REG(0x110),
577 REG(0x1c0),
578 REG(0x1c4),
579 REG(0x1c8),
580 REG(0x180),
581 REG16(0x2b4),
582 REG(0x120),
583 REG(0x124),
587 REG16(0x3a8),
588 REG16(0x28c),
589 REG16(0x288),
590 REG16(0x284),
591 REG16(0x280),
592 REG16(0x27c),
593 REG16(0x278),
594 REG16(0x274),
595 REG16(0x270),
598 REG(0x1b0),
599 REG16(0x5a8),
600 REG16(0x5ac),
603 LRI(1, 0),
604 REG(0x0c8),
654 return 0x70; in lrc_ring_mi_mode()
656 return 0x60; in lrc_ring_mi_mode()
658 return 0x54; in lrc_ring_mi_mode()
660 return 0x58; in lrc_ring_mi_mode()
668 return 0x80; in lrc_ring_bb_offset()
670 return 0x70; in lrc_ring_bb_offset()
672 return 0x64; in lrc_ring_bb_offset()
675 return 0xc4; in lrc_ring_bb_offset()
683 return 0x84; in lrc_ring_gpr0()
685 return 0x74; in lrc_ring_gpr0()
687 return 0x68; in lrc_ring_gpr0()
689 return 0xd8; in lrc_ring_gpr0()
697 return 0x12; in lrc_ring_wa_bb_per_ctx()
699 return 0x18; in lrc_ring_wa_bb_per_ctx()
709 if (x < 0) in lrc_ring_indirect_ptr()
720 if (x < 0) in lrc_ring_indirect_offset()
734 return 0xc6; in lrc_ring_cmd_buf_cctl()
738 return 0xb6; in lrc_ring_cmd_buf_cctl()
740 return 0xaa; in lrc_ring_cmd_buf_cctl()
801 regs[loc + 1] = 0; in init_common_regs()
814 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01; in init_wa_bb_regs()
837 ASSIGN_CTX_PDP(ppgtt, regs, 0); in init_ppgtt_regs()
877 memset(regs, 0, PAGE_SIZE); in __lrc_init_regs()
954 shmem_read(engine->default_state, 0, in lrc_init_state()
961 memset(state, 0, PAGE_SIZE); in lrc_init_state()
965 memset(state + context_wa_bb_offset(ce), 0, PAGE_SIZE); in lrc_init_state()
984 *cs++ = 0; in setup_predicate_disable_wa()
985 *cs++ = 0; /* No predication */ in setup_predicate_disable_wa()
987 /* predicated end, only terminates if SET_PREDICATE_RESULT:0 is clear */ in setup_predicate_disable_wa()
994 *cs++ = 0; in setup_predicate_disable_wa()
1089 return 0; in lrc_alloc()
1138 return 0; in lrc_pin()
1184 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_timestamp_wa()
1187 *cs++ = 0; in gen12_emit_timestamp_wa()
1192 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_timestamp_wa()
1193 *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0)); in gen12_emit_timestamp_wa()
1198 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_timestamp_wa()
1199 *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0)); in gen12_emit_timestamp_wa()
1212 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_restore_scratch()
1215 *cs++ = 0; in gen12_emit_restore_scratch()
1228 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_cmd_buf_wa()
1231 *cs++ = 0; in gen12_emit_cmd_buf_wa()
1236 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_cmd_buf_wa()
1237 *cs++ = i915_mmio_reg_offset(RING_CMD_BUF_CCTL(0)); in gen12_emit_cmd_buf_wa()
1252 *cs++ = 0x21; in dg2_emit_rcs_hang_wabb()
1267 * 0x3FF. However this register is not saved/restored properly by the
1270 * in this register should remain at 0 (the hardware default).
1277 *cs++ = REG_FIELD_PREP(VERT_WM_VAL, 0x3FF); in dg2_emit_draw_watermark_setting()
1297 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0); in gen12_emit_indirect_ctx_rcs()
1323 0); in gen12_emit_indirect_ctx_xcs()
1367 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template)
1371 * bits 55-63: group ID, currently unused and set to 0
1517 *batch++ = 0; in gen8_emit_flush_coherentl3_wa()
1521 *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES; in gen8_emit_flush_coherentl3_wa()
1526 0); in gen8_emit_flush_coherentl3_wa()
1532 *batch++ = 0; in gen8_emit_flush_coherentl3_wa()
1611 0), in gen9_init_indirectctx_bb()
1661 *batch++ = 0x00777000; in gen9_init_indirectctx_bb()
1662 *batch++ = 0; in gen9_init_indirectctx_bb()
1663 *batch++ = 0; in gen9_init_indirectctx_bb()
1664 *batch++ = 0; in gen9_init_indirectctx_bb()
1695 return 0; in lrc_create_wa_ctx()
1704 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0); in lrc_fini_wa_ctx()
1729 wa_bb_fn[0] = gen9_init_indirectctx_bb; in lrc_init_wa_ctx()
1733 wa_bb_fn[0] = gen8_init_indirectctx_bb; in lrc_init_wa_ctx()
1761 err = i915_ggtt_pin(wa_ctx->vma, &ww, 0, PIN_HIGH); in lrc_init_wa_ctx()
1777 for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) { in lrc_init_wa_ctx()
1790 __i915_gem_object_flush_map(wa_ctx->vma->obj, 0, batch_ptr - batch); in lrc_init_wa_ctx()
1812 memset(wa_ctx, 0, sizeof(*wa_ctx)); in lrc_init_wa_ctx()
1848 if (unlikely(dt < 0)) { in lrc_update_runtime()