Lines Matching +full:0 +full:x270
11 #define RING_EXCC(base) _MMIO((base) + 0x28)
12 #define RING_TAIL(base) _MMIO((base) + 0x30)
13 #define TAIL_ADDR 0x001FFFF8
14 #define RING_HEAD(base) _MMIO((base) + 0x34)
15 #define HEAD_WRAP_COUNT 0xFFE00000
16 #define HEAD_WRAP_ONE 0x00200000
17 #define HEAD_ADDR 0x001FFFFC
18 #define RING_START(base) _MMIO((base) + 0x38)
19 #define RING_CTL(base) _MMIO((base) + 0x3c)
21 #define RING_NR_PAGES 0x001FF000
22 #define RING_REPORT_MASK 0x00000006
23 #define RING_REPORT_64K 0x00000002
24 #define RING_REPORT_128K 0x00000004
25 #define RING_NO_REPORT 0x00000000
26 #define RING_VALID_MASK 0x00000001
27 #define RING_VALID 0x00000001
28 #define RING_INVALID 0x00000000
29 #define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */
32 #define RING_SYNC_0(base) _MMIO((base) + 0x40)
33 #define RING_SYNC_1(base) _MMIO((base) + 0x44)
34 #define RING_SYNC_2(base) _MMIO((base) + 0x48)
47 #define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
54 #define GEN6_PSMI_SLEEP_MSG_DISABLE REG_BIT(0)
55 #define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
56 #define PWRCTX_MAXCNT(base) _MMIO((base) + 0x54)
57 #define IDLE_TIME_MASK 0xFFFFF
58 #define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
59 #define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */
60 #define RING_IPEIR(base) _MMIO((base) + 0x64)
61 #define RING_IPEHR(base) _MMIO((base) + 0x68)
62 #define RING_INSTDONE(base) _MMIO((base) + 0x6c)
63 #define RING_INSTPS(base) _MMIO((base) + 0x70)
64 #define RING_DMA_FADD(base) _MMIO((base) + 0x78)
65 #define RING_ACTHD(base) _MMIO((base) + 0x74)
66 #define RING_HWS_PGA(base) _MMIO((base) + 0x80)
67 #define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84)
68 #define IPEIR(base) _MMIO((base) + 0x88)
69 #define IPEHR(base) _MMIO((base) + 0x8c)
70 #define RING_ID(base) _MMIO((base) + 0x8c)
71 #define RING_NOPID(base) _MMIO((base) + 0x94)
72 #define RING_HWSTAM(base) _MMIO((base) + 0x98)
73 #define RING_MI_MODE(base) _MMIO((base) + 0x9c)
80 #define RING_IMR(base) _MMIO((base) + 0xa8)
81 #define RING_EIR(base) _MMIO((base) + 0xb0)
82 #define RING_EMR(base) _MMIO((base) + 0xb4)
83 #define RING_ESR(base) _MMIO((base) + 0xb8)
84 #define RING_INSTPM(base) _MMIO((base) + 0xc0)
85 #define RING_CMD_CCTL(base) _MMIO((base) + 0xc4)
86 #define ACTHD(base) _MMIO((base) + 0xc8)
87 #define GEN8_R_PWR_CLK_STATE(base) _MMIO((base) + 0xc8)
91 #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
93 #define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT)
96 #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
98 #define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT)
99 #define GEN8_RPCS_EU_MIN_SHIFT 0
100 #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
102 #define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
105 #define RESET_CTL_REQUEST_RESET REG_BIT(0)
106 #define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0)
107 #define RING_BBSTATE(base) _MMIO((base) + 0x110)
109 #define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */
110 #define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */
111 #define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */
112 #define RING_BBADDR(base) _MMIO((base) + 0x140)
113 #define RING_BB_OFFSET(base) _MMIO((base) + 0x158)
114 #define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */
115 #define CCID(base) _MMIO((base) + 0x180)
116 #define CCID_EN BIT(0)
119 #define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */
120 #define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */
121 #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */
122 #define ECOSKPD(base) _MMIO((base) + 0x1d0)
126 #define ECO_FLIP_DONE REG_BIT(0)
129 #define BLIT_CCTL(base) _MMIO((base) + 0x204)
131 #define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
138 #define RING_CSCMDOP(base) _MMIO((base) + 0x20c)
143 * 6:0 == default MOCS value for reads => 6:1 == table index for reads.
145 * 15:14 == Reserved => 31:30 are set to 0.
148 #define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0)
155 #define RING_PREDICATE_RESULT(base) _MMIO((base) + 0x3b8) /* gen12+ */
157 #define MI_PREDICATE_RESULT_2(base) _MMIO((base) + 0x3bc)
158 #define LOWER_SLICE_ENABLED (1 << 0)
159 #define LOWER_SLICE_DISABLED (0 << 0)
160 #define MI_PREDICATE_SRC0(base) _MMIO((base) + 0x400)
161 #define MI_PREDICATE_SRC0_UDW(base) _MMIO((base) + 0x400 + 4)
162 #define MI_PREDICATE_SRC1(base) _MMIO((base) + 0x408)
163 #define MI_PREDICATE_SRC1_UDW(base) _MMIO((base) + 0x408 + 4)
164 #define MI_PREDICATE_DATA(base) _MMIO((base) + 0x410)
165 #define MI_PREDICATE_RESULT(base) _MMIO((base) + 0x418)
166 #define MI_PREDICATE_RESULT_1(base) _MMIO((base) + 0x41c)
168 #define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)
169 #define PP_DIR_DCLV_2G 0xffffffff
170 #define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228)
171 #define RING_ELSP(base) _MMIO((base) + 0x230)
172 #define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
173 #define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
174 #define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
175 #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0)
180 #define RING_CTX_SR_CTL(base) _MMIO((base) + 0x244)
181 #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
182 #define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)
183 #define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
184 #define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
195 #define GFX_FORWARD_VBLANK_NEVER (0 << 5)
199 #define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
200 #define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)
201 #define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)
202 #define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */
203 #define RING_PREDICATE_RESULT(base) _MMIO((base) + 0x3b8)
204 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
207 #define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28) /* CFL+ & Gen11+ */
212 #define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */
213 #define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
214 #define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
215 #define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
216 #define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0)
223 #define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)
224 #define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518)
225 #define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)
226 #define EL_CTRL_LOAD REG_BIT(0)
229 #define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8)
230 #define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4)
232 #define GEN11_VCS_SFC_FORCED_LOCK(base) _MMIO((base) + 0x88c)
233 #define GEN11_VCS_SFC_FORCED_LOCK_BIT (1 << 0)
234 #define GEN11_VCS_SFC_LOCK_STATUS(base) _MMIO((base) + 0x890)
235 #define GEN11_VCS_SFC_USAGE_BIT (1 << 0)
238 #define GEN11_VECS_SFC_FORCED_LOCK(base) _MMIO((base) + 0x201c)
239 #define GEN11_VECS_SFC_FORCED_LOCK_BIT (1 << 0)
240 #define GEN11_VECS_SFC_LOCK_ACK(base) _MMIO((base) + 0x2018)
241 #define GEN11_VECS_SFC_LOCK_ACK_BIT (1 << 0)
242 #define GEN11_VECS_SFC_USAGE(base) _MMIO((base) + 0x2014)
243 #define GEN11_VECS_SFC_USAGE_BIT (1 << 0)
245 #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
247 #define GEN12_HCP_SFC_LOCK_STATUS(base) _MMIO((base) + 0x2914)
249 #define GEN12_HCP_SFC_USAGE_BIT REG_BIT(0)
251 #define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10)
254 #define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18)