Lines Matching full:engine
250 * intel_engine_context_size() - return the size of the context for an engine
252 * @class: engine class
254 * Each engine class may require a different amount of space for a context
257 * Return: size (in bytes) of an engine class specific context image
348 static void __sprint_engine_name(struct intel_engine_cs *engine) in __sprint_engine_name() argument
351 * Before we know what the uABI name for this engine will be, in __sprint_engine_name()
352 * we still would like to keep track of this engine in the debug logs. in __sprint_engine_name()
355 GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u", in __sprint_engine_name()
356 intel_engine_class_repr(engine->class), in __sprint_engine_name()
357 engine->instance) >= sizeof(engine->name)); in __sprint_engine_name()
360 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask) in intel_engine_set_hwsp_writemask() argument
364 * per-engine HWSTAM until gen6. in intel_engine_set_hwsp_writemask()
366 if (GRAPHICS_VER(engine->i915) < 6 && engine->class != RENDER_CLASS) in intel_engine_set_hwsp_writemask()
369 if (GRAPHICS_VER(engine->i915) >= 3) in intel_engine_set_hwsp_writemask()
370 ENGINE_WRITE(engine, RING_HWSTAM, mask); in intel_engine_set_hwsp_writemask()
372 ENGINE_WRITE16(engine, RING_HWSTAM, mask); in intel_engine_set_hwsp_writemask()
375 static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine) in intel_engine_sanitize_mmio() argument
378 intel_engine_set_hwsp_writemask(engine, ~0u); in intel_engine_sanitize_mmio()
381 static void nop_irq_handler(struct intel_engine_cs *engine, u16 iir) in nop_irq_handler() argument
443 struct intel_engine_cs *engine; in intel_engine_setup() local
451 if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine))) in intel_engine_setup()
463 engine = kzalloc(sizeof(*engine), GFP_KERNEL); in intel_engine_setup()
464 if (!engine) in intel_engine_setup()
467 BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES); in intel_engine_setup()
469 INIT_LIST_HEAD(&engine->pinned_contexts_list); in intel_engine_setup()
470 engine->id = id; in intel_engine_setup()
471 engine->legacy_idx = INVALID_ENGINE; in intel_engine_setup()
472 engine->mask = BIT(id); in intel_engine_setup()
473 engine->reset_domain = get_reset_domain(GRAPHICS_VER(gt->i915), in intel_engine_setup()
475 engine->i915 = i915; in intel_engine_setup()
476 engine->gt = gt; in intel_engine_setup()
477 engine->uncore = gt->uncore; in intel_engine_setup()
479 engine->guc_id = MAKE_GUC_ID(guc_class, info->instance); in intel_engine_setup()
480 engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases); in intel_engine_setup()
482 engine->irq_handler = nop_irq_handler; in intel_engine_setup()
484 engine->class = info->class; in intel_engine_setup()
485 engine->instance = info->instance; in intel_engine_setup()
486 engine->logical_mask = BIT(logical_instance); in intel_engine_setup()
487 __sprint_engine_name(engine); in intel_engine_setup()
489 engine->props.heartbeat_interval_ms = in intel_engine_setup()
491 engine->props.max_busywait_duration_ns = in intel_engine_setup()
493 engine->props.preempt_timeout_ms = in intel_engine_setup()
495 engine->props.stop_timeout_ms = in intel_engine_setup()
497 engine->props.timeslice_duration_ms = in intel_engine_setup()
501 if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS) in intel_engine_setup()
502 engine->props.preempt_timeout_ms = 0; in intel_engine_setup()
504 if ((engine->class == COMPUTE_CLASS && !RCS_MASK(engine->gt) && in intel_engine_setup()
505 __ffs(CCS_MASK(engine->gt)) == engine->instance) || in intel_engine_setup()
506 engine->class == RENDER_CLASS) in intel_engine_setup()
507 engine->flags |= I915_ENGINE_FIRST_RENDER_COMPUTE; in intel_engine_setup()
510 if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) { in intel_engine_setup()
511 engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE; in intel_engine_setup()
512 engine->flags |= I915_ENGINE_HAS_EU_PRIORITY; in intel_engine_setup()
515 engine->defaults = engine->props; /* never to change again */ in intel_engine_setup()
517 engine->context_size = intel_engine_context_size(gt, engine->class); in intel_engine_setup()
518 if (WARN_ON(engine->context_size > BIT(20))) in intel_engine_setup()
519 engine->context_size = 0; in intel_engine_setup()
520 if (engine->context_size) in intel_engine_setup()
523 ewma__engine_latency_init(&engine->latency); in intel_engine_setup()
524 seqcount_init(&engine->stats.execlists.lock); in intel_engine_setup()
526 ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier); in intel_engine_setup()
529 intel_engine_sanitize_mmio(engine); in intel_engine_setup()
531 gt->engine_class[info->class][info->instance] = engine; in intel_engine_setup()
532 gt->engine[id] = engine; in intel_engine_setup()
537 static void __setup_engine_capabilities(struct intel_engine_cs *engine) in __setup_engine_capabilities() argument
539 struct drm_i915_private *i915 = engine->i915; in __setup_engine_capabilities()
541 if (engine->class == VIDEO_DECODE_CLASS) { in __setup_engine_capabilities()
543 * HEVC support is present on first engine instance in __setup_engine_capabilities()
547 (GRAPHICS_VER(i915) >= 9 && engine->instance == 0)) in __setup_engine_capabilities()
548 engine->uabi_capabilities |= in __setup_engine_capabilities()
552 * SFC block is present only on even logical engine in __setup_engine_capabilities()
556 (engine->gt->info.vdbox_sfc_access & in __setup_engine_capabilities()
557 BIT(engine->instance))) || in __setup_engine_capabilities()
558 (GRAPHICS_VER(i915) >= 9 && engine->instance == 0)) in __setup_engine_capabilities()
559 engine->uabi_capabilities |= in __setup_engine_capabilities()
561 } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) { in __setup_engine_capabilities()
563 engine->gt->info.sfc_mask & BIT(engine->instance)) in __setup_engine_capabilities()
564 engine->uabi_capabilities |= in __setup_engine_capabilities()
571 struct intel_engine_cs *engine; in intel_setup_engine_capabilities() local
574 for_each_engine(engine, gt, id) in intel_setup_engine_capabilities()
575 __setup_engine_capabilities(engine); in intel_setup_engine_capabilities()
584 struct intel_engine_cs *engine; in intel_engines_release() local
588 * Before we release the resources held by engine, we must be certain in intel_engines_release()
601 for_each_engine(engine, gt, id) { in intel_engines_release()
602 if (!engine->release) in intel_engines_release()
605 intel_wakeref_wait_for_idle(&engine->wakeref); in intel_engines_release()
606 GEM_BUG_ON(intel_engine_pm_is_awake(engine)); in intel_engines_release()
608 engine->release(engine); in intel_engines_release()
609 engine->release = NULL; in intel_engines_release()
611 memset(&engine->reset, 0, sizeof(engine->reset)); in intel_engines_release()
615 void intel_engine_free_request_pool(struct intel_engine_cs *engine) in intel_engine_free_request_pool() argument
617 if (!engine->request_pool) in intel_engine_free_request_pool()
620 kmem_cache_free(i915_request_slab_cache(), engine->request_pool); in intel_engine_free_request_pool()
625 struct intel_engine_cs *engine; in intel_engines_free() local
631 for_each_engine(engine, gt, id) { in intel_engines_free()
632 intel_engine_free_request_pool(engine); in intel_engines_free()
633 kfree(engine); in intel_engines_free()
634 gt->engine[id] = NULL; in intel_engines_free()
752 * engine is not available for use. in engine_mask_apply_compute_fuses()
795 * the blitter forcewake domain to read the engine fuses, but at the same time
798 * domains based on the full engine mask in the platform capabilities before
859 * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers
922 void intel_engine_init_execlists(struct intel_engine_cs *engine) in intel_engine_init_execlists() argument
924 struct intel_engine_execlists * const execlists = &engine->execlists; in intel_engine_init_execlists()
935 static void cleanup_status_page(struct intel_engine_cs *engine) in cleanup_status_page() argument
940 intel_engine_set_hwsp_writemask(engine, ~0u); in cleanup_status_page()
942 vma = fetch_and_zero(&engine->status_page.vma); in cleanup_status_page()
946 if (!HWS_NEEDS_PHYSICAL(engine->i915)) in cleanup_status_page()
953 static int pin_ggtt_status_page(struct intel_engine_cs *engine, in pin_ggtt_status_page() argument
959 if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt)) in pin_ggtt_status_page()
978 static int init_status_page(struct intel_engine_cs *engine) in init_status_page() argument
986 INIT_LIST_HEAD(&engine->status_page.timelines); in init_status_page()
995 obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); in init_status_page()
997 drm_err(&engine->i915->drm, in init_status_page()
1004 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); in init_status_page()
1013 if (!ret && !HWS_NEEDS_PHYSICAL(engine->i915)) in init_status_page()
1014 ret = pin_ggtt_status_page(engine, &ww, vma); in init_status_page()
1024 engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE); in init_status_page()
1025 engine->status_page.vma = vma; in init_status_page()
1043 static int engine_setup_common(struct intel_engine_cs *engine) in engine_setup_common() argument
1047 init_llist_head(&engine->barrier_tasks); in engine_setup_common()
1049 err = init_status_page(engine); in engine_setup_common()
1053 engine->breadcrumbs = intel_breadcrumbs_create(engine); in engine_setup_common()
1054 if (!engine->breadcrumbs) { in engine_setup_common()
1059 engine->sched_engine = i915_sched_engine_create(ENGINE_PHYSICAL); in engine_setup_common()
1060 if (!engine->sched_engine) { in engine_setup_common()
1064 engine->sched_engine->private_data = engine; in engine_setup_common()
1066 err = intel_engine_init_cmd_parser(engine); in engine_setup_common()
1070 intel_engine_init_execlists(engine); in engine_setup_common()
1071 intel_engine_init__pm(engine); in engine_setup_common()
1072 intel_engine_init_retire(engine); in engine_setup_common()
1075 engine->sseu = in engine_setup_common()
1076 intel_sseu_from_device_info(&engine->gt->info.sseu); in engine_setup_common()
1078 intel_engine_init_workarounds(engine); in engine_setup_common()
1079 intel_engine_init_whitelist(engine); in engine_setup_common()
1080 intel_engine_init_ctx_wa(engine); in engine_setup_common()
1082 if (GRAPHICS_VER(engine->i915) >= 12) in engine_setup_common()
1083 engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO; in engine_setup_common()
1088 i915_sched_engine_put(engine->sched_engine); in engine_setup_common()
1090 intel_breadcrumbs_put(engine->breadcrumbs); in engine_setup_common()
1092 cleanup_status_page(engine); in engine_setup_common()
1104 struct intel_engine_cs *engine = ce->engine; in measure_breadcrumb_dw() local
1108 GEM_BUG_ON(!engine->gt->scratch); in measure_breadcrumb_dw()
1114 frame->rq.engine = engine; in measure_breadcrumb_dw()
1128 spin_lock_irq(&engine->sched_engine->lock); in measure_breadcrumb_dw()
1130 dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs; in measure_breadcrumb_dw()
1132 spin_unlock_irq(&engine->sched_engine->lock); in measure_breadcrumb_dw()
1142 intel_engine_create_pinned_context(struct intel_engine_cs *engine, in intel_engine_create_pinned_context() argument
1152 ce = intel_context_create(engine); in intel_engine_create_pinned_context()
1170 list_add_tail(&ce->pinned_contexts_link, &engine->pinned_contexts_list); in intel_engine_create_pinned_context()
1185 struct intel_engine_cs *engine = ce->engine; in intel_engine_destroy_pinned_context() local
1186 struct i915_vma *hwsp = engine->status_page.vma; in intel_engine_destroy_pinned_context()
1200 create_kernel_context(struct intel_engine_cs *engine) in create_kernel_context() argument
1204 return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K, in create_kernel_context()
1211 * @engine: Engine to initialize.
1213 * Initializes @engine@ structure members shared between legacy and execlists
1216 * Typcally done at later stages of submission mode specific engine setup.
1220 static int engine_init_common(struct intel_engine_cs *engine) in engine_init_common() argument
1225 engine->set_default_submission(engine); in engine_init_common()
1235 ce = create_kernel_context(engine); in engine_init_common()
1243 engine->emit_fini_breadcrumb_dw = ret; in engine_init_common()
1244 engine->kernel_context = ce; in engine_init_common()
1255 int (*setup)(struct intel_engine_cs *engine); in intel_engines_init()
1256 struct intel_engine_cs *engine; in intel_engines_init() local
1271 for_each_engine(engine, gt, id) { in intel_engines_init()
1272 err = engine_setup_common(engine); in intel_engines_init()
1276 err = setup(engine); in intel_engines_init()
1280 err = engine_init_common(engine); in intel_engines_init()
1284 intel_engine_add_user(engine); in intel_engines_init()
1291 * intel_engines_cleanup_common - cleans up the engine state created by
1293 * @engine: Engine to cleanup.
1297 void intel_engine_cleanup_common(struct intel_engine_cs *engine) in intel_engine_cleanup_common() argument
1299 GEM_BUG_ON(!list_empty(&engine->sched_engine->requests)); in intel_engine_cleanup_common()
1301 i915_sched_engine_put(engine->sched_engine); in intel_engine_cleanup_common()
1302 intel_breadcrumbs_put(engine->breadcrumbs); in intel_engine_cleanup_common()
1304 intel_engine_fini_retire(engine); in intel_engine_cleanup_common()
1305 intel_engine_cleanup_cmd_parser(engine); in intel_engine_cleanup_common()
1307 if (engine->default_state) in intel_engine_cleanup_common()
1308 fput(engine->default_state); in intel_engine_cleanup_common()
1310 if (engine->kernel_context) in intel_engine_cleanup_common()
1311 intel_engine_destroy_pinned_context(engine->kernel_context); in intel_engine_cleanup_common()
1313 GEM_BUG_ON(!llist_empty(&engine->barrier_tasks)); in intel_engine_cleanup_common()
1314 cleanup_status_page(engine); in intel_engine_cleanup_common()
1316 intel_wa_list_free(&engine->ctx_wa_list); in intel_engine_cleanup_common()
1317 intel_wa_list_free(&engine->wa_list); in intel_engine_cleanup_common()
1318 intel_wa_list_free(&engine->whitelist); in intel_engine_cleanup_common()
1322 * intel_engine_resume - re-initializes the HW state of the engine
1323 * @engine: Engine to resume.
1327 int intel_engine_resume(struct intel_engine_cs *engine) in intel_engine_resume() argument
1329 intel_engine_apply_workarounds(engine); in intel_engine_resume()
1330 intel_engine_apply_whitelist(engine); in intel_engine_resume()
1332 return engine->resume(engine); in intel_engine_resume()
1335 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine) in intel_engine_get_active_head() argument
1337 struct drm_i915_private *i915 = engine->i915; in intel_engine_get_active_head()
1342 acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW); in intel_engine_get_active_head()
1344 acthd = ENGINE_READ(engine, RING_ACTHD); in intel_engine_get_active_head()
1346 acthd = ENGINE_READ(engine, ACTHD); in intel_engine_get_active_head()
1351 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine) in intel_engine_get_last_batch_head() argument
1355 if (GRAPHICS_VER(engine->i915) >= 8) in intel_engine_get_last_batch_head()
1356 bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW); in intel_engine_get_last_batch_head()
1358 bbaddr = ENGINE_READ(engine, RING_BBADDR); in intel_engine_get_last_batch_head()
1363 static unsigned long stop_timeout(const struct intel_engine_cs *engine) in stop_timeout() argument
1370 * the engine to quiesce. We've stopped submission to the engine, and in stop_timeout()
1372 * leave the engine idle. So they should not be caught unaware by in stop_timeout()
1375 return READ_ONCE(engine->props.stop_timeout_ms); in stop_timeout()
1378 static int __intel_engine_stop_cs(struct intel_engine_cs *engine, in __intel_engine_stop_cs() argument
1382 struct intel_uncore *uncore = engine->uncore; in __intel_engine_stop_cs()
1383 const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); in __intel_engine_stop_cs()
1392 if (IS_GRAPHICS_VER(engine->i915, 11, 12)) in __intel_engine_stop_cs()
1393 intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base), in __intel_engine_stop_cs()
1396 err = __intel_wait_for_register_fw(engine->uncore, mode, in __intel_engine_stop_cs()
1407 int intel_engine_stop_cs(struct intel_engine_cs *engine) in intel_engine_stop_cs() argument
1411 if (GRAPHICS_VER(engine->i915) < 3) in intel_engine_stop_cs()
1414 ENGINE_TRACE(engine, "\n"); in intel_engine_stop_cs()
1427 if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) { in intel_engine_stop_cs()
1428 ENGINE_TRACE(engine, in intel_engine_stop_cs()
1430 ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR, in intel_engine_stop_cs()
1431 ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR); in intel_engine_stop_cs()
1438 if ((ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) != in intel_engine_stop_cs()
1439 (ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR)) in intel_engine_stop_cs()
1446 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine) in intel_engine_cancel_stop_cs() argument
1448 ENGINE_TRACE(engine, "\n"); in intel_engine_cancel_stop_cs()
1450 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); in intel_engine_cancel_stop_cs()
1453 static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine) in __cs_pending_mi_force_wakes() argument
1477 if (!_reg[engine->id].reg) { in __cs_pending_mi_force_wakes()
1478 drm_err(&engine->i915->drm, in __cs_pending_mi_force_wakes()
1479 "MSG IDLE undefined for engine id %u\n", engine->id); in __cs_pending_mi_force_wakes()
1483 val = intel_uncore_read(engine->uncore, _reg[engine->id]); in __cs_pending_mi_force_wakes()
1517 void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine) in intel_engine_wait_for_pending_mi_fw() argument
1519 u32 fw_pending = __cs_pending_mi_force_wakes(engine); in intel_engine_wait_for_pending_mi_fw()
1522 __gpm_wait_for_fw_complete(engine->gt, fw_pending); in intel_engine_wait_for_pending_mi_fw()
1526 void intel_engine_get_instdone(const struct intel_engine_cs *engine, in intel_engine_get_instdone() argument
1529 struct drm_i915_private *i915 = engine->i915; in intel_engine_get_instdone()
1530 struct intel_uncore *uncore = engine->uncore; in intel_engine_get_instdone()
1531 u32 mmio_base = engine->mmio_base; in intel_engine_get_instdone()
1542 if (engine->id != RCS0) in intel_engine_get_instdone()
1554 for_each_ss_steering(iter, engine->gt, slice, subslice) { in intel_engine_get_instdone()
1556 intel_gt_mcr_read(engine->gt, in intel_engine_get_instdone()
1560 intel_gt_mcr_read(engine->gt, in intel_engine_get_instdone()
1566 for_each_ss_steering(iter, engine->gt, slice, subslice) in intel_engine_get_instdone()
1568 intel_gt_mcr_read(engine->gt, in intel_engine_get_instdone()
1576 if (engine->id != RCS0) in intel_engine_get_instdone()
1588 if (engine->id == RCS0) in intel_engine_get_instdone()
1597 static bool ring_is_idle(struct intel_engine_cs *engine) in ring_is_idle() argument
1601 if (I915_SELFTEST_ONLY(!engine->mmio_base)) in ring_is_idle()
1604 if (!intel_engine_pm_get_if_awake(engine)) in ring_is_idle()
1608 if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) != in ring_is_idle()
1609 (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR)) in ring_is_idle()
1613 if (GRAPHICS_VER(engine->i915) > 2 && in ring_is_idle()
1614 !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE)) in ring_is_idle()
1617 intel_engine_pm_put(engine); in ring_is_idle()
1622 void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync) in __intel_engine_flush_submission() argument
1624 struct tasklet_struct *t = &engine->sched_engine->tasklet; in __intel_engine_flush_submission()
1644 * intel_engine_is_idle() - Report if the engine has finished process all work
1645 * @engine: the intel_engine_cs
1648 * to hardware, and that the engine is idle.
1650 bool intel_engine_is_idle(struct intel_engine_cs *engine) in intel_engine_is_idle() argument
1653 if (intel_gt_is_wedged(engine->gt)) in intel_engine_is_idle()
1656 if (!intel_engine_pm_is_awake(engine)) in intel_engine_is_idle()
1660 intel_synchronize_hardirq(engine->i915); in intel_engine_is_idle()
1661 intel_engine_flush_submission(engine); in intel_engine_is_idle()
1664 if (!i915_sched_engine_is_empty(engine->sched_engine)) in intel_engine_is_idle()
1668 return ring_is_idle(engine); in intel_engine_is_idle()
1673 struct intel_engine_cs *engine; in intel_engines_are_idle() local
1687 for_each_engine(engine, gt, id) { in intel_engines_are_idle()
1688 if (!intel_engine_is_idle(engine)) in intel_engines_are_idle()
1695 bool intel_engine_irq_enable(struct intel_engine_cs *engine) in intel_engine_irq_enable() argument
1697 if (!engine->irq_enable) in intel_engine_irq_enable()
1701 spin_lock(engine->gt->irq_lock); in intel_engine_irq_enable()
1702 engine->irq_enable(engine); in intel_engine_irq_enable()
1703 spin_unlock(engine->gt->irq_lock); in intel_engine_irq_enable()
1708 void intel_engine_irq_disable(struct intel_engine_cs *engine) in intel_engine_irq_disable() argument
1710 if (!engine->irq_disable) in intel_engine_irq_disable()
1714 spin_lock(engine->gt->irq_lock); in intel_engine_irq_disable()
1715 engine->irq_disable(engine); in intel_engine_irq_disable()
1716 spin_unlock(engine->gt->irq_lock); in intel_engine_irq_disable()
1721 struct intel_engine_cs *engine; in intel_engines_reset_default_submission() local
1724 for_each_engine(engine, gt, id) { in intel_engines_reset_default_submission()
1725 if (engine->sanitize) in intel_engines_reset_default_submission()
1726 engine->sanitize(engine); in intel_engines_reset_default_submission()
1728 engine->set_default_submission(engine); in intel_engines_reset_default_submission()
1732 bool intel_engine_can_store_dword(struct intel_engine_cs *engine) in intel_engine_can_store_dword() argument
1734 switch (GRAPHICS_VER(engine->i915)) { in intel_engine_can_store_dword()
1739 return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915)); in intel_engine_can_store_dword()
1741 return !IS_I965G(engine->i915); /* who knows! */ in intel_engine_can_store_dword()
1743 return engine->class != VIDEO_DECODE_CLASS; /* b0rked */ in intel_engine_can_store_dword()
1754 * Even though we are holding the engine->sched_engine->lock here, there in get_timeline()
1832 static void intel_engine_print_registers(struct intel_engine_cs *engine, in intel_engine_print_registers() argument
1835 struct drm_i915_private *dev_priv = engine->i915; in intel_engine_print_registers()
1836 struct intel_engine_execlists * const execlists = &engine->execlists; in intel_engine_print_registers()
1839 if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(dev_priv, 4, 7)) in intel_engine_print_registers()
1840 drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID)); in intel_engine_print_registers()
1843 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI)); in intel_engine_print_registers()
1845 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO)); in intel_engine_print_registers()
1848 ENGINE_READ(engine, RING_START)); in intel_engine_print_registers()
1850 ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR); in intel_engine_print_registers()
1852 ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR); in intel_engine_print_registers()
1854 ENGINE_READ(engine, RING_CTL), in intel_engine_print_registers()
1855 ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : ""); in intel_engine_print_registers()
1856 if (GRAPHICS_VER(engine->i915) > 2) { in intel_engine_print_registers()
1858 ENGINE_READ(engine, RING_MI_MODE), in intel_engine_print_registers()
1859 ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : ""); in intel_engine_print_registers()
1864 ENGINE_READ(engine, RING_IMR)); in intel_engine_print_registers()
1866 ENGINE_READ(engine, RING_ESR)); in intel_engine_print_registers()
1868 ENGINE_READ(engine, RING_EMR)); in intel_engine_print_registers()
1870 ENGINE_READ(engine, RING_EIR)); in intel_engine_print_registers()
1873 addr = intel_engine_get_active_head(engine); in intel_engine_print_registers()
1876 addr = intel_engine_get_last_batch_head(engine); in intel_engine_print_registers()
1880 addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW); in intel_engine_print_registers()
1882 addr = ENGINE_READ(engine, RING_DMA_FADD); in intel_engine_print_registers()
1884 addr = ENGINE_READ(engine, DMA_FADD_I8XX); in intel_engine_print_registers()
1889 ENGINE_READ(engine, RING_IPEIR)); in intel_engine_print_registers()
1891 ENGINE_READ(engine, RING_IPEHR)); in intel_engine_print_registers()
1893 drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR)); in intel_engine_print_registers()
1894 drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR)); in intel_engine_print_registers()
1897 if (HAS_EXECLISTS(dev_priv) && !intel_engine_uses_guc(engine)) { in intel_engine_print_registers()
1900 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX]; in intel_engine_print_registers()
1906 str_yes_no(test_bit(TASKLET_STATE_SCHED, &engine->sched_engine->tasklet.state)), in intel_engine_print_registers()
1907 str_enabled_disabled(!atomic_read(&engine->sched_engine->tasklet.count)), in intel_engine_print_registers()
1908 repr_timer(&engine->execlists.preempt), in intel_engine_print_registers()
1909 repr_timer(&engine->execlists.timer)); in intel_engine_print_registers()
1915 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO), in intel_engine_print_registers()
1916 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI), in intel_engine_print_registers()
1931 i915_sched_engine_active_lock_bh(engine->sched_engine); in intel_engine_print_registers()
1962 i915_sched_engine_active_unlock_bh(engine->sched_engine); in intel_engine_print_registers()
1965 ENGINE_READ(engine, RING_PP_DIR_BASE)); in intel_engine_print_registers()
1967 ENGINE_READ(engine, RING_PP_DIR_BASE_READ)); in intel_engine_print_registers()
1969 ENGINE_READ(engine, RING_PP_DIR_DCLV)); in intel_engine_print_registers()
2023 static void print_properties(struct intel_engine_cs *engine, in print_properties() argument
2031 .offset = offsetof(typeof(engine->props), x), \ in print_properties()
2049 read_ul(&engine->props, p->offset), in print_properties()
2050 read_ul(&engine->defaults, p->offset)); in print_properties()
2101 msg = "\t\tactive on engine"; in intel_engine_dump_active_requests()
2109 static void engine_dump_active_requests(struct intel_engine_cs *engine, struct drm_printer *m) in engine_dump_active_requests() argument
2116 * No need for an engine->irq_seqno_barrier() before the seqno reads. in engine_dump_active_requests()
2122 lockdep_assert_held(&engine->sched_engine->lock); in engine_dump_active_requests()
2126 guc = intel_uc_uses_guc_submission(&engine->gt->uc); in engine_dump_active_requests()
2128 ce = intel_engine_get_hung_context(engine); in engine_dump_active_requests()
2132 hung_rq = intel_engine_execlist_find_hung_request(engine); in engine_dump_active_requests()
2139 intel_guc_dump_active_requests(engine, hung_rq, m); in engine_dump_active_requests()
2141 intel_engine_dump_active_requests(&engine->sched_engine->requests, in engine_dump_active_requests()
2145 void intel_engine_dump(struct intel_engine_cs *engine, in intel_engine_dump() argument
2149 struct i915_gpu_error * const error = &engine->i915->gpu_error; in intel_engine_dump()
2163 if (intel_gt_is_wedged(engine->gt)) in intel_engine_dump()
2166 drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count)); in intel_engine_dump()
2168 str_yes_no(!llist_empty(&engine->barrier_tasks))); in intel_engine_dump()
2170 ewma__engine_latency_read(&engine->latency)); in intel_engine_dump()
2171 if (intel_engine_supports_stats(engine)) in intel_engine_dump()
2173 ktime_to_ms(intel_engine_get_busy_time(engine, in intel_engine_dump()
2176 engine->fw_domain, READ_ONCE(engine->fw_active)); in intel_engine_dump()
2179 rq = READ_ONCE(engine->heartbeat.systole); in intel_engine_dump()
2185 i915_reset_engine_count(error, engine), in intel_engine_dump()
2187 print_properties(engine, m); in intel_engine_dump()
2189 spin_lock_irqsave(&engine->sched_engine->lock, flags); in intel_engine_dump()
2190 engine_dump_active_requests(engine, m); in intel_engine_dump()
2193 list_count(&engine->sched_engine->hold)); in intel_engine_dump()
2194 spin_unlock_irqrestore(&engine->sched_engine->lock, flags); in intel_engine_dump()
2196 drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base); in intel_engine_dump()
2197 wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm); in intel_engine_dump()
2199 intel_engine_print_registers(engine, m); in intel_engine_dump()
2200 intel_runtime_pm_put(engine->uncore->rpm, wakeref); in intel_engine_dump()
2205 intel_execlists_show_requests(engine, m, i915_request_show, 8); in intel_engine_dump()
2208 hexdump(m, engine->status_page.addr, PAGE_SIZE); in intel_engine_dump()
2210 drm_printf(m, "Idle? %s\n", str_yes_no(intel_engine_is_idle(engine))); in intel_engine_dump()
2212 intel_engine_print_breadcrumbs(engine, m); in intel_engine_dump()
2216 * intel_engine_get_busy_time() - Return current accumulated engine busyness
2217 * @engine: engine to report on
2220 * Returns accumulated time @engine was busy since engine stats were enabled.
2222 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now) in intel_engine_get_busy_time() argument
2224 return engine->busyness(engine, now); in intel_engine_get_busy_time()
2242 intel_engine_execlist_find_hung_request(struct intel_engine_cs *engine) in intel_engine_execlist_find_hung_request() argument
2251 GEM_BUG_ON(intel_uc_uses_guc_submission(&engine->gt->uc)); in intel_engine_execlist_find_hung_request()
2254 * We are called by the error capture, reset and to dump engine in intel_engine_execlist_find_hung_request()
2260 * not need an engine->irq_seqno_barrier() before the seqno reads. in intel_engine_execlist_find_hung_request()
2264 lockdep_assert_held(&engine->sched_engine->lock); in intel_engine_execlist_find_hung_request()
2267 request = execlists_active(&engine->execlists); in intel_engine_execlist_find_hung_request()
2282 list_for_each_entry(request, &engine->sched_engine->requests, in intel_engine_execlist_find_hung_request()
2294 void xehp_enable_ccs_engines(struct intel_engine_cs *engine) in xehp_enable_ccs_engines() argument
2299 * so for simplicity we'll take care of this in the RCS engine's in xehp_enable_ccs_engines()
2304 if (!CCS_MASK(engine->gt)) in xehp_enable_ccs_engines()
2307 intel_uncore_write(engine->uncore, GEN12_RCU_MODE, in xehp_enable_ccs_engines()