Lines Matching +full:mipi +full:- +full:mode
86 struct drm_encoder *encoder = &intel_dsi->base.base; in vlv_dsi_wait_for_fifo_empty()
87 struct drm_device *dev = encoder->dev; in vlv_dsi_wait_for_fifo_empty()
96 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n"); in vlv_dsi_wait_for_fifo_empty()
108 for (j = 0; j < min_t(u32, len - i, 4); j++) in write_data()
124 for (j = 0; j < min_t(u32, len - i, 4); j++) in read_data()
133 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; in intel_dsi_host_transfer()
135 enum port port = intel_dsi_host->port; in intel_dsi_host_transfer()
149 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { in intel_dsi_host_transfer()
165 drm_err(&dev_priv->drm, in intel_dsi_host_transfer()
172 if (msg->rx_len) { in intel_dsi_host_transfer()
179 drm_err(&dev_priv->drm, in intel_dsi_host_transfer()
186 /* ->rx_len is set only for reads */ in intel_dsi_host_transfer()
187 if (msg->rx_len) { in intel_dsi_host_transfer()
191 drm_err(&dev_priv->drm, in intel_dsi_host_transfer()
194 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); in intel_dsi_host_transfer()
220 * send a video mode command
227 struct drm_encoder *encoder = &intel_dsi->base.base; in dpi_send_cmd()
228 struct drm_device *dev = encoder->dev; in dpi_send_cmd()
243 drm_dbg_kms(&dev_priv->drm, in dpi_send_cmd()
250 drm_err(&dev_priv->drm, in dpi_send_cmd()
251 "Video mode command 0x%08x send failed.\n", cmd); in dpi_send_cmd()
274 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_compute_config()
277 struct intel_connector *intel_connector = intel_dsi->attached_connector; in intel_dsi_compute_config()
278 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dsi_compute_config()
281 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_compute_config()
282 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_dsi_compute_config()
292 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in intel_dsi_compute_config()
293 return -EINVAL; in intel_dsi_compute_config()
295 /* DSI uses short packets for sync events, so clear mode flags for DSI */ in intel_dsi_compute_config()
296 adjusted_mode->flags = 0; in intel_dsi_compute_config()
298 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) in intel_dsi_compute_config()
299 pipe_config->pipe_bpp = 24; in intel_dsi_compute_config()
301 pipe_config->pipe_bpp = 18; in intel_dsi_compute_config()
305 pipe_config->mode_flags |= in intel_dsi_compute_config()
309 if (intel_dsi->ports == BIT(PORT_C)) in intel_dsi_compute_config()
310 pipe_config->cpu_transcoder = TRANSCODER_DSI_C; in intel_dsi_compute_config()
312 pipe_config->cpu_transcoder = TRANSCODER_DSI_A; in intel_dsi_compute_config()
316 return -EINVAL; in intel_dsi_compute_config()
320 return -EINVAL; in intel_dsi_compute_config()
323 pipe_config->clock_set = true; in intel_dsi_compute_config()
330 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in glk_dsi_enable_io()
336 /* Set the MIPI mode in glk_dsi_enable_io()
338 * Power ON MIPI IO first and then write into IO reset and LP wake bits in glk_dsi_enable_io()
340 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enable_io()
352 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enable_io()
362 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enable_io()
365 drm_err(&dev_priv->drm, "MIPIO port is powergated\n"); in glk_dsi_enable_io()
369 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enable_io()
379 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in glk_dsi_device_ready()
384 /* Wait for MIPI PHY status bit to set */ in glk_dsi_device_ready()
385 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_device_ready()
388 drm_err(&dev_priv->drm, "PHY is not ON\n"); in glk_dsi_device_ready()
397 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_device_ready()
414 drm_err(&dev_priv->drm, "ULPS not active\n"); in glk_dsi_device_ready()
422 /* Enter Normal Mode */ in glk_dsi_device_ready()
435 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_device_ready()
438 drm_err(&dev_priv->drm, in glk_dsi_device_ready()
443 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_device_ready()
446 drm_err(&dev_priv->drm, in glk_dsi_device_ready()
447 "D-PHY not entering LP-11 state\n"); in glk_dsi_device_ready()
453 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bxt_dsi_device_ready()
458 drm_dbg_kms(&dev_priv->drm, "\n"); in bxt_dsi_device_ready()
460 /* Enable MIPI PHY transparent latch */ in bxt_dsi_device_ready()
461 for_each_dsi_port(port, intel_dsi->ports) { in bxt_dsi_device_ready()
469 for_each_dsi_port(port, intel_dsi->ports) { in bxt_dsi_device_ready()
481 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_dsi_device_ready()
486 drm_dbg_kms(&dev_priv->drm, "\n"); in vlv_dsi_device_ready()
497 for_each_dsi_port(port, intel_dsi->ports) { in vlv_dsi_device_ready()
503 /* Enable MIPI PHY transparent latch in vlv_dsi_device_ready()
504 * Common bit for both MIPI Port A & MIPI Port C in vlv_dsi_device_ready()
505 * No similar bit in MIPI Port C reg in vlv_dsi_device_ready()
524 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_device_ready()
536 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in glk_dsi_enter_low_power_mode()
542 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enter_low_power_mode()
549 /* Wait for MIPI PHY status bit to unset */ in glk_dsi_enter_low_power_mode()
550 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enter_low_power_mode()
553 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); in glk_dsi_enter_low_power_mode()
557 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enter_low_power_mode()
560 drm_err(&dev_priv->drm, in glk_dsi_enter_low_power_mode()
561 "MIPI IO Port is not powergated\n"); in glk_dsi_enter_low_power_mode()
567 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in glk_dsi_disable_mipi_io()
577 /* Wait for MIPI PHY status bit to unset */ in glk_dsi_disable_mipi_io()
578 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_disable_mipi_io()
581 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); in glk_dsi_disable_mipi_io()
584 /* Clear MIPI mode */ in glk_dsi_disable_mipi_io()
585 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_disable_mipi_io()
600 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_dsi_clear_device_ready()
604 drm_dbg_kms(&dev_priv->drm, "\n"); in vlv_dsi_clear_device_ready()
605 for_each_dsi_port(port, intel_dsi->ports) { in vlv_dsi_clear_device_ready()
606 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ in vlv_dsi_clear_device_ready()
624 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI in vlv_dsi_clear_device_ready()
625 * Port A only. MIPI Port C has no similar bit for checking. in vlv_dsi_clear_device_ready()
630 drm_err(&dev_priv->drm, "DSI LP not going Low\n"); in vlv_dsi_clear_device_ready()
632 /* Disable MIPI PHY transparent latch */ in vlv_dsi_clear_device_ready()
645 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_port_enable()
646 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsi_port_enable()
650 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { in intel_dsi_port_enable()
653 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_port_enable()
657 intel_dsi->pixel_overlap << in intel_dsi_port_enable()
665 intel_dsi->pixel_overlap << in intel_dsi_port_enable()
671 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_port_enable()
681 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { in intel_dsi_port_enable()
682 temp |= (intel_dsi->dual_link - 1) in intel_dsi_port_enable()
687 temp |= crtc->pipe ? in intel_dsi_port_enable()
692 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888) in intel_dsi_port_enable()
703 struct drm_device *dev = encoder->base.dev; in intel_dsi_port_disable()
708 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_port_disable()
713 /* de-assert ip_tg_enable signal */ in intel_dsi_port_disable()
727 intel_dsi->panel_power_off_time); in intel_dsi_wait_panel_power_cycle()
729 if (panel_power_off_duration < (s64)intel_dsi->panel_pwr_cycle_delay) in intel_dsi_wait_panel_power_cycle()
730 msleep(intel_dsi->panel_pwr_cycle_delay - panel_power_off_duration); in intel_dsi_wait_panel_power_cycle()
744 * Steps starting with MIPI refer to VBT sequences, note that for v2
748 * v2 video mode seq v3 video mode seq command mode seq
749 * - power on - MIPIPanelPowerOn - power on
750 * - wait t1+t2 - wait t1+t2
751 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin
752 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11
753 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds
754 * - MIPITearOn
755 * - MIPIDisplayOn
756 * - turn on DPI - turn on DPI - set pipe to dsr mode
757 * - MIPIDisplayOn - MIPIDisplayOn
758 * - wait t5 - wait t5
759 * - backlight on - MIPIBacklightOn - backlight on
761 * - backlight off - MIPIBacklightOff - backlight off
762 * - wait t6 - wait t6
763 * - MIPIDisplayOff
764 * - turn off DPI - turn off DPI - disable pipe dsr mode
765 * - MIPITearOff
766 * - MIPIDisplayOff - MIPIDisplayOff
767 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00
768 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin
769 * - wait t3 - wait t3
770 * - power off - MIPIPanelPowerOff - power off
771 * - wait t4 - wait t4
784 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_dsi_pre_enable()
785 struct intel_connector *connector = to_intel_connector(conn_state->connector); in intel_dsi_pre_enable()
786 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_dsi_pre_enable()
787 enum pipe pipe = crtc->pipe; in intel_dsi_pre_enable()
792 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_pre_enable()
811 /* Add MIPI IO reset programming for modeset */ in intel_dsi_pre_enable()
836 * Give the panel time to power-on and then deassert its reset. in intel_dsi_pre_enable()
837 * Depending on the VBT MIPI sequences version the deassert-seq in intel_dsi_pre_enable()
839 * the delay in that case. If there is no deassert-seq, then an in intel_dsi_pre_enable()
840 * unconditional msleep is used to give the panel time to power-on. in intel_dsi_pre_enable()
842 if (connector->panel.vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) { in intel_dsi_pre_enable()
843 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); in intel_dsi_pre_enable()
846 msleep(intel_dsi->panel_on_delay); in intel_dsi_pre_enable()
857 /* Put device in ready state (LP-11) */ in intel_dsi_pre_enable()
864 /* Send initialization commands in LP mode */ in intel_dsi_pre_enable()
868 * Enable port in pre-enable phase itself because as per hw team in intel_dsi_pre_enable()
872 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_pre_enable()
879 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_pre_enable()
897 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); in bxt_dsi_enable()
911 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_dsi_disable()
915 drm_dbg_kms(&i915->drm, "\n"); in intel_dsi_disable()
926 /* Send Shutdown command to the panel in LP mode */ in intel_dsi_disable()
927 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_disable()
935 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_clear_device_ready()
948 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_post_disable()
953 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_post_disable()
962 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_post_disable()
979 /* Transition to LP-00 */ in intel_dsi_post_disable()
988 /* Add MIPI IO reset programming for modeset */ in intel_dsi_post_disable()
1009 intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay); in intel_dsi_post_disable()
1012 intel_dsi->panel_power_off_time = ktime_get_boottime(); in intel_dsi_post_disable()
1025 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_get_hw_state()
1031 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_get_hw_state()
1034 encoder->power_domain); in intel_dsi_get_hw_state()
1041 * machine. See BSpec North Display Engine registers/MIPI[BXT]. in intel_dsi_get_hw_state()
1048 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_get_hw_state()
1062 /* Try command mode if video mode not enabled */ in intel_dsi_get_hw_state()
1080 if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C)) in intel_dsi_get_hw_state()
1093 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in intel_dsi_get_hw_state()
1101 struct drm_device *dev = encoder->base.dev; in bxt_dsi_get_pipe_config()
1104 &pipe_config->hw.adjusted_mode; in bxt_dsi_get_pipe_config()
1106 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in bxt_dsi_get_pipe_config()
1108 unsigned int lane_count = intel_dsi->lane_count; in bxt_dsi_get_pipe_config()
1117 adjusted_mode_sw = &crtc->config->hw.adjusted_mode; in bxt_dsi_get_pipe_config()
1120 * Atleast one port is active as encoder->get_config called only if in bxt_dsi_get_pipe_config()
1121 * encoder->get_hw_state() returns true. in bxt_dsi_get_pipe_config()
1123 for_each_dsi_port(port, intel_dsi->ports) { in bxt_dsi_get_pipe_config()
1132 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); in bxt_dsi_get_pipe_config()
1135 pipe_config->mode_flags |= in bxt_dsi_get_pipe_config()
1139 adjusted_mode->crtc_hdisplay = in bxt_dsi_get_pipe_config()
1142 adjusted_mode->crtc_vdisplay = in bxt_dsi_get_pipe_config()
1145 adjusted_mode->crtc_vtotal = in bxt_dsi_get_pipe_config()
1149 hactive = adjusted_mode->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1153 * Meaningful for video mode non-burst sync pulse mode only, in bxt_dsi_get_pipe_config()
1154 * can be zero for non-burst sync events and burst modes in bxt_dsi_get_pipe_config()
1161 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1163 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1165 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1167 if (intel_dsi->dual_link) { in bxt_dsi_get_pipe_config()
1178 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; in bxt_dsi_get_pipe_config()
1179 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1180 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; in bxt_dsi_get_pipe_config()
1181 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1182 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; in bxt_dsi_get_pipe_config()
1184 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; in bxt_dsi_get_pipe_config()
1185 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; in bxt_dsi_get_pipe_config()
1186 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; in bxt_dsi_get_pipe_config()
1187 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; in bxt_dsi_get_pipe_config()
1201 hfp_sw = adjusted_mode_sw->crtc_hsync_start - in bxt_dsi_get_pipe_config()
1202 adjusted_mode_sw->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1203 hsync_sw = adjusted_mode_sw->crtc_hsync_end - in bxt_dsi_get_pipe_config()
1204 adjusted_mode_sw->crtc_hsync_start; in bxt_dsi_get_pipe_config()
1205 hbp_sw = adjusted_mode_sw->crtc_htotal - in bxt_dsi_get_pipe_config()
1206 adjusted_mode_sw->crtc_hsync_end; in bxt_dsi_get_pipe_config()
1208 if (intel_dsi->dual_link) { in bxt_dsi_get_pipe_config()
1215 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1217 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1219 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1221 /* Reverse calculating the adjusted mode parameters from port reg vals*/ in bxt_dsi_get_pipe_config()
1223 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1225 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1227 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1229 if (intel_dsi->dual_link) { in bxt_dsi_get_pipe_config()
1235 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + in bxt_dsi_get_pipe_config()
1237 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1239 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1242 if (adjusted_mode->crtc_htotal == crtc_htotal_sw) in bxt_dsi_get_pipe_config()
1243 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal; in bxt_dsi_get_pipe_config()
1245 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw) in bxt_dsi_get_pipe_config()
1246 adjusted_mode->crtc_hsync_start = in bxt_dsi_get_pipe_config()
1247 adjusted_mode_sw->crtc_hsync_start; in bxt_dsi_get_pipe_config()
1249 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw) in bxt_dsi_get_pipe_config()
1250 adjusted_mode->crtc_hsync_end = in bxt_dsi_get_pipe_config()
1251 adjusted_mode_sw->crtc_hsync_end; in bxt_dsi_get_pipe_config()
1253 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw) in bxt_dsi_get_pipe_config()
1254 adjusted_mode->crtc_hblank_start = in bxt_dsi_get_pipe_config()
1255 adjusted_mode_sw->crtc_hblank_start; in bxt_dsi_get_pipe_config()
1257 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw) in bxt_dsi_get_pipe_config()
1258 adjusted_mode->crtc_hblank_end = in bxt_dsi_get_pipe_config()
1259 adjusted_mode_sw->crtc_hblank_end; in bxt_dsi_get_pipe_config()
1265 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_get_config()
1269 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_get_config()
1271 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); in intel_dsi_get_config()
1280 pipe_config->port_clock = pclk; in intel_dsi_get_config()
1282 /* FIXME definitely not right for burst/cmd mode/pixel overlap */ in intel_dsi_get_config()
1283 pipe_config->hw.adjusted_mode.crtc_clock = pclk; in intel_dsi_get_config()
1284 if (intel_dsi->dual_link) in intel_dsi_get_config()
1285 pipe_config->hw.adjusted_mode.crtc_clock *= 2; in intel_dsi_get_config()
1305 struct drm_device *dev = encoder->dev; in set_dsi_timings()
1309 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in set_dsi_timings()
1310 unsigned int lane_count = intel_dsi->lane_count; in set_dsi_timings()
1314 hactive = adjusted_mode->crtc_hdisplay; in set_dsi_timings()
1315 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; in set_dsi_timings()
1316 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; in set_dsi_timings()
1317 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; in set_dsi_timings()
1319 if (intel_dsi->dual_link) { in set_dsi_timings()
1321 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) in set_dsi_timings()
1322 hactive += intel_dsi->pixel_overlap; in set_dsi_timings()
1328 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; in set_dsi_timings()
1329 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; in set_dsi_timings()
1330 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; in set_dsi_timings()
1334 intel_dsi->burst_mode_ratio); in set_dsi_timings()
1335 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); in set_dsi_timings()
1337 intel_dsi->burst_mode_ratio); in set_dsi_timings()
1338 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); in set_dsi_timings()
1340 for_each_dsi_port(port, intel_dsi->ports) { in set_dsi_timings()
1343 * Program hdisplay and vdisplay on MIPI transcoder. in set_dsi_timings()
1349 adjusted_mode->crtc_hdisplay); in set_dsi_timings()
1351 adjusted_mode->crtc_vdisplay); in set_dsi_timings()
1353 adjusted_mode->crtc_vtotal); in set_dsi_timings()
1360 /* meaningful for video mode non-burst sync pulse mode only, in set_dsi_timings()
1361 * can be zero for non-burst sync events and burst modes */ in set_dsi_timings()
1394 struct drm_encoder *encoder = &intel_encoder->base; in intel_dsi_prepare()
1395 struct drm_device *dev = encoder->dev; in intel_dsi_prepare()
1397 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_dsi_prepare()
1399 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dsi_prepare()
1401 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in intel_dsi_prepare()
1405 drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(crtc->pipe)); in intel_dsi_prepare()
1407 mode_hdisplay = adjusted_mode->crtc_hdisplay; in intel_dsi_prepare()
1409 if (intel_dsi->dual_link) { in intel_dsi_prepare()
1411 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) in intel_dsi_prepare()
1412 mode_hdisplay += intel_dsi->pixel_overlap; in intel_dsi_prepare()
1415 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_prepare()
1432 enum pipe pipe = crtc->pipe; in intel_dsi_prepare()
1446 intel_dsi->dphy_reg); in intel_dsi_prepare()
1449 …adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT… in intel_dsi_prepare()
1454 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; in intel_dsi_prepare()
1456 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; in intel_dsi_prepare()
1459 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; in intel_dsi_prepare()
1460 val |= pixel_format_to_reg(intel_dsi->pixel_format); in intel_dsi_prepare()
1464 if (intel_dsi->eotp_pkt == 0) in intel_dsi_prepare()
1466 if (intel_dsi->clock_stop) in intel_dsi_prepare()
1475 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_prepare()
1482 * In burst mode, value greater than one DPI line Time in byte in intel_dsi_prepare()
1486 * In non-burst mode, Value greater than one DPI frame time in in intel_dsi_prepare()
1490 * In DBI only mode, value greater than one DBI frame time in in intel_dsi_prepare()
1496 intel_dsi->video_mode == BURST_MODE) { in intel_dsi_prepare()
1498 …txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) +… in intel_dsi_prepare()
1501 …txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, i… in intel_dsi_prepare()
1504 intel_dsi->lp_rx_timeout); in intel_dsi_prepare()
1506 intel_dsi->turn_arnd_val); in intel_dsi_prepare()
1508 intel_dsi->rst_timer_val); in intel_dsi_prepare()
1514 txclkesc(intel_dsi->escape_clk_div, 100)); in intel_dsi_prepare()
1517 !intel_dsi->dual_link) { in intel_dsi_prepare()
1522 * if not in dual link mode. in intel_dsi_prepare()
1526 intel_dsi->init_count); in intel_dsi_prepare()
1534 intel_dsi->init_count); in intel_dsi_prepare()
1542 intel_dsi->hs_to_lp_count); in intel_dsi_prepare()
1551 intel_dsi->lp_byte_clk); in intel_dsi_prepare()
1555 intel_dsi->lp_byte_clk); in intel_dsi_prepare()
1558 intel_dsi->dphy_reg); in intel_dsi_prepare()
1567 intel_dsi->bw_timer); in intel_dsi_prepare()
1570 …intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_… in intel_dsi_prepare()
1573 u32 fmt = intel_dsi->video_frmt_cfg_bits | IP_TG_CONFIG; in intel_dsi_prepare()
1582 switch (intel_dsi->video_mode) { in intel_dsi_prepare()
1584 MISSING_CASE(intel_dsi->video_mode); in intel_dsi_prepare()
1604 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_unprepare()
1612 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_unprepare()
1662 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); in vlv_dsi_add_properties()
1671 drm_connector_attach_scaling_mode_property(&connector->base, in vlv_dsi_add_properties()
1674 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; in vlv_dsi_add_properties()
1676 drm_connector_set_panel_orientation_with_quirk(&connector->base, in vlv_dsi_add_properties()
1678 fixed_mode->hdisplay, in vlv_dsi_add_properties()
1679 fixed_mode->vdisplay); in vlv_dsi_add_properties()
1691 struct drm_device *dev = intel_dsi->base.base.dev; in vlv_dphy_param_init()
1693 struct intel_connector *connector = intel_dsi->attached_connector; in vlv_dphy_param_init()
1694 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; in vlv_dphy_param_init()
1705 switch (intel_dsi->lane_count) { in vlv_dphy_param_init()
1723 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero; in vlv_dphy_param_init()
1724 ths_prepare_hszero = mipi_config->ths_prepare_hszero; in vlv_dphy_param_init()
1730 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num); in vlv_dphy_param_init()
1742 ths_prepare_ns = max(mipi_config->ths_prepare, in vlv_dphy_param_init()
1743 mipi_config->tclk_prepare); in vlv_dphy_param_init()
1749 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n", in vlv_dphy_param_init()
1756 (ths_prepare_hszero - ths_prepare_ns) * ui_den, in vlv_dphy_param_init()
1770 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n", in vlv_dphy_param_init()
1777 (tclk_prepare_clkzero - ths_prepare_ns) in vlv_dphy_param_init()
1781 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n", in vlv_dphy_param_init()
1787 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); in vlv_dphy_param_init()
1791 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n", in vlv_dphy_param_init()
1797 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 | in vlv_dphy_param_init()
1804 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count in vlv_dphy_param_init()
1818 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); in vlv_dphy_param_init()
1820 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch); in vlv_dphy_param_init()
1821 intel_dsi->hs_to_lp_count += extra_byte_count; in vlv_dphy_param_init()
1824 /* LP -> HS for clock lanes in vlv_dphy_param_init()
1832 intel_dsi->clk_lp_to_hs_count = in vlv_dphy_param_init()
1838 intel_dsi->clk_lp_to_hs_count += extra_byte_count; in vlv_dphy_param_init()
1840 /* HS->LP for Clock Lanes in vlv_dphy_param_init()
1847 intel_dsi->clk_hs_to_lp_count = in vlv_dphy_param_init()
1850 intel_dsi->clk_hs_to_lp_count += extra_byte_count; in vlv_dphy_param_init()
1857 struct drm_device *dev = &dev_priv->drm; in vlv_dsi_init()
1867 drm_dbg_kms(&dev_priv->drm, "\n"); in vlv_dsi_init()
1869 /* There is no detection method for MIPI so rely on VBT */ in vlv_dsi_init()
1874 dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE; in vlv_dsi_init()
1876 dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE; in vlv_dsi_init()
1888 intel_encoder = &intel_dsi->base; in vlv_dsi_init()
1889 encoder = &intel_encoder->base; in vlv_dsi_init()
1890 intel_dsi->attached_connector = intel_connector; in vlv_dsi_init()
1892 connector = &intel_connector->base; in vlv_dsi_init()
1897 intel_encoder->compute_config = intel_dsi_compute_config; in vlv_dsi_init()
1898 intel_encoder->pre_enable = intel_dsi_pre_enable; in vlv_dsi_init()
1900 intel_encoder->enable = bxt_dsi_enable; in vlv_dsi_init()
1901 intel_encoder->disable = intel_dsi_disable; in vlv_dsi_init()
1902 intel_encoder->post_disable = intel_dsi_post_disable; in vlv_dsi_init()
1903 intel_encoder->get_hw_state = intel_dsi_get_hw_state; in vlv_dsi_init()
1904 intel_encoder->get_config = intel_dsi_get_config; in vlv_dsi_init()
1905 intel_encoder->update_pipe = intel_backlight_update; in vlv_dsi_init()
1906 intel_encoder->shutdown = intel_dsi_shutdown; in vlv_dsi_init()
1908 intel_connector->get_hw_state = intel_connector_get_hw_state; in vlv_dsi_init()
1910 intel_encoder->port = port; in vlv_dsi_init()
1911 intel_encoder->type = INTEL_OUTPUT_DSI; in vlv_dsi_init()
1912 intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI; in vlv_dsi_init()
1913 intel_encoder->cloneable = 0; in vlv_dsi_init()
1916 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI in vlv_dsi_init()
1920 intel_encoder->pipe_mask = ~0; in vlv_dsi_init()
1922 intel_encoder->pipe_mask = BIT(PIPE_A); in vlv_dsi_init()
1924 intel_encoder->pipe_mask = BIT(PIPE_B); in vlv_dsi_init()
1926 intel_dsi->panel_power_off_time = ktime_get_boottime(); in vlv_dsi_init()
1928 intel_bios_init_panel(dev_priv, &intel_connector->panel, NULL, NULL); in vlv_dsi_init()
1930 if (intel_connector->panel.vbt.dsi.config->dual_link) in vlv_dsi_init()
1931 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); in vlv_dsi_init()
1933 intel_dsi->ports = BIT(port); in vlv_dsi_init()
1935 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) in vlv_dsi_init()
1936 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; in vlv_dsi_init()
1938 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) in vlv_dsi_init()
1939 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; in vlv_dsi_init()
1942 for_each_dsi_port(port, intel_dsi->ports) { in vlv_dsi_init()
1950 intel_dsi->dsi_hosts[port] = host; in vlv_dsi_init()
1954 drm_dbg_kms(&dev_priv->drm, "no device found\n"); in vlv_dsi_init()
1958 /* Use clock read-back from current hw-state for fastboot */ in vlv_dsi_init()
1961 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n", in vlv_dsi_init()
1962 intel_dsi->pclk, current_mode->clock); in vlv_dsi_init()
1963 if (intel_fuzzy_clock_check(intel_dsi->pclk, in vlv_dsi_init()
1964 current_mode->clock)) { in vlv_dsi_init()
1965 drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n"); in vlv_dsi_init()
1966 intel_dsi->pclk = current_mode->clock; in vlv_dsi_init()
1982 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ in vlv_dsi_init()
1983 connector->interlace_allowed = false; in vlv_dsi_init()
1984 connector->doublescan_allowed = false; in vlv_dsi_init()
1988 mutex_lock(&dev->mode_config.mutex); in vlv_dsi_init()
1990 mutex_unlock(&dev->mode_config.mutex); in vlv_dsi_init()
1993 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n"); in vlv_dsi_init()
2006 drm_connector_cleanup(&intel_connector->base); in vlv_dsi_init()
2008 drm_encoder_cleanup(&intel_encoder->base); in vlv_dsi_init()