Lines Matching +full:0 +full:- +full:19
1 // SPDX-License-Identifier: MIT
21 ROW_INDEX_6BPP = 0,
30 COLUMN_INDEX_8BPC = 0,
63 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
64 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
65 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
66 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
71 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
72 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
73 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
74 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
75 { 17, 18, -12 }
79 { 768, 15, 6144, 11, 21, 19, 19, {
80 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
81 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
82 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
83 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
84 { 21, 22, -12 }
89 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
90 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
91 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
92 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
93 { 25, 26, -12 }
97 { 768, 15, 6144, 19, 29, 27, 27, {
98 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
99 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
100 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
101 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
102 { 29, 30, -12 }
109 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
110 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
111 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
112 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
117 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
118 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
119 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
120 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
124 { 512, 12, 6144, 11, 20, 19, 19, {
125 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
126 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
127 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
128 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
129 { 21, 23, -12 }
134 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
135 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
136 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
137 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
138 { 24, 25, -12 }
142 { 512, 12, 6144, 19, 28, 27, 27, {
143 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
144 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
145 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
146 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
147 { 28, 29, -12 }
154 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
155 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
156 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
157 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
162 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
163 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
164 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
165 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
169 { 410, 15, 5632, 11, 20, 19, 19, {
170 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
171 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
172 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
173 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
174 { 19, 20, -12 }
179 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
180 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
181 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
182 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
183 { 23, 24, -12 }
187 { 410, 15, 5632, 19, 28, 27, 27, {
188 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
189 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
190 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
191 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
192 { 27, 28, -12 }
199 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
200 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
201 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
202 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
207 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
208 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
209 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
210 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
214 { 341, 15, 2048, 11, 20, 19, 19, {
215 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
216 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
217 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
218 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
219 { 21, 23, -12 }
224 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
225 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
226 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
227 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
228 { 22, 23, -12 }
232 { 341, 15, 2048, 19, 28, 27, 27, {
233 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
234 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
235 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
236 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
237 { 26, 27, -12 }
244 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
245 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
246 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
247 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
252 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
253 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
254 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
255 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
259 { 273, 15, 2048, 11, 20, 19, 19, {
260 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
261 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
262 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
263 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
264 { 16, 17, -12 }
269 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
270 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
271 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
272 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
273 { 20, 21, -12 }
277 { 273, 15, 2048, 19, 28, 27, 27, {
278 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
279 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
280 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
281 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
282 { 24, 25, -12 }
303 return -EINVAL; in get_row_index_for_rc_params()
321 return -EINVAL; in get_column_index_for_rc_params()
331 if (row_index < 0) in get_rc_params()
335 if (column_index < 0) in get_rc_params()
343 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsc_source_support()
344 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_dsc_source_support()
345 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_dsc_source_support()
347 if (!RUNTIME_INFO(i915)->has_dsc) in intel_dsc_source_support()
361 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in is_pipe_dsc()
372 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A); in is_pipe_dsc()
381 int bpc = vdsc_cfg->bits_per_component; in calculate_rc_params()
382 int bpp = vdsc_cfg->bits_per_pixel >> 4; in calculate_rc_params()
384 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 in calculate_rc_params()
387 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 in calculate_rc_params()
390 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 in calculate_rc_params()
393 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 in calculate_rc_params()
395 int qp_bpc_modifier = (bpc - 8) * 2; in calculate_rc_params()
398 if (vdsc_cfg->slice_height >= 8) in calculate_rc_params()
399 rc->first_line_bpg_offset = in calculate_rc_params()
400 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100); in calculate_rc_params()
402 rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1); in calculate_rc_params()
406 rc->initial_offset = 2048; in calculate_rc_params()
408 rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2); in calculate_rc_params()
410 rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2); in calculate_rc_params()
412 rc->initial_offset = 6144; in calculate_rc_params()
415 rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp); in calculate_rc_params()
417 rc->flatness_min_qp = 3 + qp_bpc_modifier; in calculate_rc_params()
418 rc->flatness_max_qp = 12 + qp_bpc_modifier; in calculate_rc_params()
420 rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier; in calculate_rc_params()
421 rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier; in calculate_rc_params()
423 bpp_i = (2 * (bpp - 6)); in calculate_rc_params()
424 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) { in calculate_rc_params()
426 rc->rc_range_params[buf_i].range_min_qp = in calculate_rc_params()
428 rc->rc_range_params[buf_i].range_max_qp = in calculate_rc_params()
433 rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i]; in calculate_rc_params()
435 res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2); in calculate_rc_params()
436 rc->rc_range_params[buf_i].range_bpg_offset = in calculate_rc_params()
439 rc->rc_range_params[buf_i].range_bpg_offset = in calculate_rc_params()
442 res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3); in calculate_rc_params()
443 rc->rc_range_params[buf_i].range_bpg_offset = in calculate_rc_params()
446 rc->rc_range_params[buf_i].range_bpg_offset = in calculate_rc_params()
454 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_dsc_compute_params()
455 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_dsc_compute_params()
456 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; in intel_dsc_compute_params()
457 u16 compressed_bpp = pipe_config->dsc.compressed_bpp; in intel_dsc_compute_params()
460 u8 i = 0; in intel_dsc_compute_params()
462 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; in intel_dsc_compute_params()
463 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, in intel_dsc_compute_params()
464 pipe_config->dsc.slice_count); in intel_dsc_compute_params()
467 vdsc_cfg->simple_422 = false; in intel_dsc_compute_params()
469 vdsc_cfg->vbr_enable = false; in intel_dsc_compute_params()
472 vdsc_cfg->bits_per_pixel = compressed_bpp << 4; in intel_dsc_compute_params()
473 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; in intel_dsc_compute_params()
475 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { in intel_dsc_compute_params()
477 * six 0s are appended to the lsb of each threshold value in intel_dsc_compute_params()
481 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6; in intel_dsc_compute_params()
489 vdsc_cfg->rc_buf_thresh[12] = 0x7C; in intel_dsc_compute_params()
490 vdsc_cfg->rc_buf_thresh[13] = 0x7D; in intel_dsc_compute_params()
495 * upto uncompressed bpp-1, hence add calculations for all the rc in intel_dsc_compute_params()
501 return -ENOMEM; in intel_dsc_compute_params()
507 vdsc_cfg->bits_per_component); in intel_dsc_compute_params()
509 return -EINVAL; in intel_dsc_compute_params()
512 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset; in intel_dsc_compute_params()
513 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay; in intel_dsc_compute_params()
514 vdsc_cfg->initial_offset = rc_params->initial_offset; in intel_dsc_compute_params()
515 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp; in intel_dsc_compute_params()
516 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp; in intel_dsc_compute_params()
517 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0; in intel_dsc_compute_params()
518 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1; in intel_dsc_compute_params()
520 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { in intel_dsc_compute_params()
521 vdsc_cfg->rc_range_params[i].range_min_qp = in intel_dsc_compute_params()
522 rc_params->rc_range_params[i].range_min_qp; in intel_dsc_compute_params()
523 vdsc_cfg->rc_range_params[i].range_max_qp = in intel_dsc_compute_params()
524 rc_params->rc_range_params[i].range_max_qp; in intel_dsc_compute_params()
529 vdsc_cfg->rc_range_params[i].range_bpg_offset = in intel_dsc_compute_params()
530 rc_params->rc_range_params[i].range_bpg_offset & in intel_dsc_compute_params()
539 if (vdsc_cfg->bits_per_component <= 10) in intel_dsc_compute_params()
540 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; in intel_dsc_compute_params()
542 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; in intel_dsc_compute_params()
545 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / in intel_dsc_compute_params()
546 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); in intel_dsc_compute_params()
550 return 0; in intel_dsc_compute_params()
556 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_dsc_power_domain()
557 enum pipe pipe = crtc->pipe; in intel_dsc_power_domain()
563 * - ICL eDP/DSI transcoder in intel_dsc_power_domain()
564 * - Display version 12 (except RKL) pipe A in intel_dsc_power_domain()
580 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsc_pps_configure()
581 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_dsc_pps_configure()
582 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dsc_pps_configure()
583 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_dsc_pps_configure()
584 enum pipe pipe = crtc->pipe; in intel_dsc_pps_configure()
585 u32 pps_val = 0; in intel_dsc_pps_configure()
588 u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1; in intel_dsc_pps_configure()
589 int i = 0; in intel_dsc_pps_configure()
591 if (crtc_state->bigjoiner_pipes) in intel_dsc_pps_configure()
595 pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << in intel_dsc_pps_configure()
597 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | in intel_dsc_pps_configure()
598 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT; in intel_dsc_pps_configure()
599 if (vdsc_cfg->dsc_version_minor == 2) in intel_dsc_pps_configure()
601 if (vdsc_cfg->block_pred_enable) in intel_dsc_pps_configure()
603 if (vdsc_cfg->convert_rgb) in intel_dsc_pps_configure()
605 if (vdsc_cfg->simple_422) in intel_dsc_pps_configure()
607 if (vdsc_cfg->vbr_enable) in intel_dsc_pps_configure()
609 drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
617 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
624 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
631 pps_val = 0; in intel_dsc_pps_configure()
632 pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); in intel_dsc_pps_configure()
633 drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
641 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
648 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
655 pps_val = 0; in intel_dsc_pps_configure()
656 pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | in intel_dsc_pps_configure()
657 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); in intel_dsc_pps_configure()
658 drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
666 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
673 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
680 pps_val = 0; in intel_dsc_pps_configure()
681 pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | in intel_dsc_pps_configure()
682 DSC_SLICE_WIDTH(vdsc_cfg->slice_width); in intel_dsc_pps_configure()
683 drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
691 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
698 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
705 pps_val = 0; in intel_dsc_pps_configure()
706 pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | in intel_dsc_pps_configure()
707 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); in intel_dsc_pps_configure()
708 drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
716 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
723 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
730 pps_val = 0; in intel_dsc_pps_configure()
731 pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | in intel_dsc_pps_configure()
732 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); in intel_dsc_pps_configure()
733 drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
741 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
748 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
755 pps_val = 0; in intel_dsc_pps_configure()
756 pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | in intel_dsc_pps_configure()
757 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | in intel_dsc_pps_configure()
758 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | in intel_dsc_pps_configure()
759 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); in intel_dsc_pps_configure()
760 drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
768 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
775 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
782 pps_val = 0; in intel_dsc_pps_configure()
783 pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | in intel_dsc_pps_configure()
784 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); in intel_dsc_pps_configure()
785 drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
793 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
800 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
807 pps_val = 0; in intel_dsc_pps_configure()
808 pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | in intel_dsc_pps_configure()
809 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); in intel_dsc_pps_configure()
810 drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
818 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
825 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
832 pps_val = 0; in intel_dsc_pps_configure()
833 pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | in intel_dsc_pps_configure()
835 drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
843 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
850 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
857 pps_val = 0; in intel_dsc_pps_configure()
858 pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | in intel_dsc_pps_configure()
859 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | in intel_dsc_pps_configure()
862 drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
870 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
877 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
884 pps_val = 0; in intel_dsc_pps_configure()
885 pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | in intel_dsc_pps_configure()
886 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / in intel_dsc_pps_configure()
887 vdsc_cfg->slice_width) | in intel_dsc_pps_configure()
888 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / in intel_dsc_pps_configure()
889 vdsc_cfg->slice_height); in intel_dsc_pps_configure()
890 drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
898 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
905 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
912 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword)); in intel_dsc_pps_configure()
913 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { in intel_dsc_pps_configure()
915 (u32)(vdsc_cfg->rc_buf_thresh[i] << in intel_dsc_pps_configure()
917 drm_dbg_kms(&dev_priv->drm, "RC_BUF_THRESH_%d = 0x%08x\n", i, in intel_dsc_pps_configure()
922 rc_buf_thresh_dword[0]); in intel_dsc_pps_configure()
929 if (crtc_state->dsc.dsc_split) { in intel_dsc_pps_configure()
931 rc_buf_thresh_dword[0]); in intel_dsc_pps_configure()
941 rc_buf_thresh_dword[0]); in intel_dsc_pps_configure()
948 if (crtc_state->dsc.dsc_split) { in intel_dsc_pps_configure()
951 rc_buf_thresh_dword[0]); in intel_dsc_pps_configure()
965 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword)); in intel_dsc_pps_configure()
966 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { in intel_dsc_pps_configure()
968 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << in intel_dsc_pps_configure()
970 (vdsc_cfg->rc_range_params[i].range_max_qp << in intel_dsc_pps_configure()
972 (vdsc_cfg->rc_range_params[i].range_min_qp << in intel_dsc_pps_configure()
974 drm_dbg_kms(&dev_priv->drm, "RC_RANGE_PARAM_%d = 0x%08x\n", i, in intel_dsc_pps_configure()
979 rc_range_params_dword[0]); in intel_dsc_pps_configure()
994 if (crtc_state->dsc.dsc_split) { in intel_dsc_pps_configure()
996 rc_range_params_dword[0]); in intel_dsc_pps_configure()
1018 rc_range_params_dword[0]); in intel_dsc_pps_configure()
1037 if (crtc_state->dsc.dsc_split) { in intel_dsc_pps_configure()
1040 rc_range_params_dword[0]); in intel_dsc_pps_configure()
1069 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dsc_dsi_pps_write()
1075 if (!crtc_state->dsc.compression_enable) in intel_dsc_dsi_pps_write()
1080 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsc_dsi_pps_write()
1081 dsi = intel_dsi->dsi_hosts[port]->device; in intel_dsc_dsi_pps_write()
1092 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dsc_dp_pps_write()
1095 if (!crtc_state->dsc.compression_enable) in intel_dsc_dp_pps_write()
1098 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */ in intel_dsc_dp_pps_write()
1101 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */ in intel_dsc_dp_pps_write()
1104 dig_port->write_infoframe(encoder, crtc_state, in intel_dsc_dp_pps_write()
1112 ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1; in dss_ctl1_reg()
1118 ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2; in dss_ctl2_reg()
1123 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_uncompressed_joiner_enable()
1124 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_uncompressed_joiner_enable()
1125 u32 dss_ctl1_val = 0; in intel_uncompressed_joiner_enable()
1127 if (crtc_state->bigjoiner_pipes && !crtc_state->dsc.compression_enable) { in intel_uncompressed_joiner_enable()
1133 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); in intel_uncompressed_joiner_enable()
1139 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsc_enable()
1140 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_dsc_enable()
1141 u32 dss_ctl1_val = 0; in intel_dsc_enable()
1142 u32 dss_ctl2_val = 0; in intel_dsc_enable()
1144 if (!crtc_state->dsc.compression_enable) in intel_dsc_enable()
1150 if (crtc_state->dsc.dsc_split) { in intel_dsc_enable()
1154 if (crtc_state->bigjoiner_pipes) { in intel_dsc_enable()
1159 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); in intel_dsc_enable()
1160 intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val); in intel_dsc_enable()
1165 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in intel_dsc_disable()
1166 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_dsc_disable()
1169 if (old_crtc_state->dsc.compression_enable || in intel_dsc_disable()
1170 old_crtc_state->bigjoiner_pipes) { in intel_dsc_disable()
1171 intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0); in intel_dsc_disable()
1172 intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0); in intel_dsc_disable()
1178 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsc_get_config()
1179 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_dsc_get_config()
1180 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dsc_get_config()
1181 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_dsc_get_config()
1182 enum pipe pipe = crtc->pipe; in intel_dsc_get_config()
1199 crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE; in intel_dsc_get_config()
1200 if (!crtc_state->dsc.compression_enable) in intel_dsc_get_config()
1203 crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) && in intel_dsc_get_config()
1214 vdsc_cfg->bits_per_pixel = val; in intel_dsc_get_config()
1215 crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; in intel_dsc_get_config()