124 		EDP_PSR_ERROR(intel_dp->psr.transcoder);  in psr_irq_psr_error_bit_get()
132 		EDP_PSR_POST_EXIT(intel_dp->psr.transcoder);  in psr_irq_post_exit_bit_get()
140 		EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder);  in psr_irq_pre_entry_bit_get()
148 		EDP_PSR_MASK(intel_dp->psr.transcoder);  in psr_irq_mask_get()
158 		imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);  in psr_irq_control()
213 	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;  in intel_psr_irq_handler()
219 		imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);  in intel_psr_irq_handler()
502 	val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) &  in hsw_activate_psr1()
504 	intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val);  in hsw_activate_psr1()
600 		tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));  in hsw_activate_psr2()
604 			       PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0);  in hsw_activate_psr2()
611 	intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0);  in hsw_activate_psr2()
613 	intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val);  in hsw_activate_psr2()
617 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans)  in transcoder_has_psr2()
643 	val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder));  in psr2_program_idle_frames()
646 	intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val);  in psr2_program_idle_frames()
1062 		val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));  in intel_psr_get_config()
1068 		val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder));  in intel_psr_get_config()
1079 	enum transcoder transcoder = intel_dp->psr.transcoder;  in intel_psr_activate()  local
1081 	if (transcoder_has_psr2(dev_priv, transcoder))  in intel_psr_activate()
1083 			    intel_de_read(dev_priv, EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE);  in intel_psr_activate()
1086 		    intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) & EDP_PSR_ENABLE);  in intel_psr_activate()
1118 	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;  in intel_psr_enable_source()
1135 	intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder),  in intel_psr_enable_source()
1177 				     TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),  in intel_psr_enable_source()
1217 				    TRANS_PSR_IIR(intel_dp->psr.transcoder));  in psr_interrupt_error_check()
1245 	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;  in intel_psr_enable_locked()
1276 		if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) {  in intel_psr_exit()
1278 					    EDP_PSR2_CTL(intel_dp->psr.transcoder));  in intel_psr_exit()
1283 				    EDP_PSR_CTL(intel_dp->psr.transcoder));  in intel_psr_exit()
1292 				    EDP_PSR2_CTL(intel_dp->psr.transcoder));  in intel_psr_exit()
1296 			       EDP_PSR2_CTL(intel_dp->psr.transcoder), val);  in intel_psr_exit()
1299 				    EDP_PSR_CTL(intel_dp->psr.transcoder));  in intel_psr_exit()
1303 			       EDP_PSR_CTL(intel_dp->psr.transcoder), val);  in intel_psr_exit()
1315 		psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder);  in intel_psr_wait_exit_locked()
1318 		psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder);  in intel_psr_wait_exit_locked()
1355 				     TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),  in intel_psr_disable_locked()
1502 			       PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),  in psr_force_hw_tracking_exit()
1970 				       EDP_PSR2_STATUS(intel_dp->psr.transcoder),  in _psr2_ready_for_pipe_update_locked()
1985 				       EDP_PSR_STATUS(intel_dp->psr.transcoder),  in _psr1_ready_for_pipe_update_locked()
2035 		reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder);  in __psr_wait_for_idle_locked()
2038 		reg = EDP_PSR_STATUS(intel_dp->psr.transcoder);  in __psr_wait_for_idle_locked()
2213 		intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), val);  in _psr_invalidate_handle()
2305 				intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),  in _psr_flush_handle()