123 	return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_ERROR :  in psr_irq_psr_error_bit_get()
131 	return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_POST_EXIT :  in psr_irq_post_exit_bit_get()
139 	return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_PRE_ENTRY :  in psr_irq_pre_entry_bit_get()
147 	return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_MASK :  in psr_irq_mask_get()
157 	if (DISPLAY_VER(dev_priv) >= 12)  in psr_irq_control()
218 	if (DISPLAY_VER(dev_priv) >= 12)  in intel_psr_irq_handler()
236 		if (DISPLAY_VER(dev_priv) >= 9) {  in intel_psr_irq_handler()
364 	if (DISPLAY_VER(dev_priv) >= 9 &&  in intel_psr_init_dpcd()
409 		if (DISPLAY_VER(dev_priv) >= 8)  in intel_psr_enable_sink()
427 	if (DISPLAY_VER(dev_priv) >= 11)  in intel_psr1_get_tp_time()
499 	if (DISPLAY_VER(dev_priv) >= 8)  in hsw_activate_psr1()
539 	if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)  in hsw_activate_psr2()
572 	} else if (DISPLAY_VER(dev_priv) >= 12) {  in hsw_activate_psr2()
583 	} else if (DISPLAY_VER(dev_priv) >= 9) {  in hsw_activate_psr2()
621 	else if (DISPLAY_VER(dev_priv) >= 12)  in transcoder_has_psr2()
833 	if (DISPLAY_VER(dev_priv) <= 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b)  in _compute_psr2_sdp_prior_scanline_indication()
898 	if (DISPLAY_VER(dev_priv) >= 12) {  in intel_psr2_config_valid()
902 	} else if (DISPLAY_VER(dev_priv) >= 10) {  in intel_psr2_config_valid()
906 	} else if (DISPLAY_VER(dev_priv) == 9) {  in intel_psr2_config_valid()
1067 	if (DISPLAY_VER(dev_priv) >= 12) {  in intel_psr_get_config()
1132 	if (DISPLAY_VER(dev_priv) < 11)  in intel_psr_enable_source()
1160 		if (DISPLAY_VER(dev_priv) == 9)  in intel_psr_enable_source()
1215 	if (DISPLAY_VER(dev_priv) >= 12)  in psr_interrupt_error_check()
2408 	if (DISPLAY_VER(dev_priv) < 12 && dig_port->base.port != PORT_A) {  in intel_psr_init()
2417 	if (DISPLAY_VER(dev_priv) < 12)  in intel_psr_init()