32 	mutex_lock(&dev_priv->display.pps.mutex);  in intel_pps_lock()
42 	mutex_unlock(&dev_priv->display.pps.mutex);  in intel_pps_unlock()
53 	enum pipe pipe = intel_dp->pps.pps_pipe;  in vlv_power_sequencer_kick()
139 				    intel_dp->pps.active_pipe != INVALID_PIPE &&  in vlv_find_free_pps()
140 				    intel_dp->pps.active_pipe !=  in vlv_find_free_pps()
141 				    intel_dp->pps.pps_pipe);  in vlv_find_free_pps()
143 			if (intel_dp->pps.pps_pipe != INVALID_PIPE)  in vlv_find_free_pps()
144 				pipes &= ~(1 << intel_dp->pps.pps_pipe);  in vlv_find_free_pps()
147 				    intel_dp->pps.pps_pipe != INVALID_PIPE);  in vlv_find_free_pps()
149 			if (intel_dp->pps.active_pipe != INVALID_PIPE)  in vlv_find_free_pps()
150 				pipes &= ~(1 << intel_dp->pps.active_pipe);  in vlv_find_free_pps()
167 	lockdep_assert_held(&dev_priv->display.pps.mutex);  in vlv_power_sequencer_pipe()
172 	drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE &&  in vlv_power_sequencer_pipe()
173 		    intel_dp->pps.active_pipe != intel_dp->pps.pps_pipe);  in vlv_power_sequencer_pipe()
175 	if (intel_dp->pps.pps_pipe != INVALID_PIPE)  in vlv_power_sequencer_pipe()
176 		return intel_dp->pps.pps_pipe;  in vlv_power_sequencer_pipe()
188 	intel_dp->pps.pps_pipe = pipe;  in vlv_power_sequencer_pipe()
192 		    pipe_name(intel_dp->pps.pps_pipe),  in vlv_power_sequencer_pipe()
206 	return intel_dp->pps.pps_pipe;  in vlv_power_sequencer_pipe()
216 	lockdep_assert_held(&dev_priv->display.pps.mutex);  in bxt_power_sequencer_idx()
221 	if (!intel_dp->pps.pps_reset)  in bxt_power_sequencer_idx()
224 	intel_dp->pps.pps_reset = false;  in bxt_power_sequencer_idx()
286 	lockdep_assert_held(&dev_priv->display.pps.mutex);  in vlv_initial_power_sequencer_setup()
290 	intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,  in vlv_initial_power_sequencer_setup()
293 	if (intel_dp->pps.pps_pipe == INVALID_PIPE)  in vlv_initial_power_sequencer_setup()
294 		intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,  in vlv_initial_power_sequencer_setup()
297 	if (intel_dp->pps.pps_pipe == INVALID_PIPE)  in vlv_initial_power_sequencer_setup()
298 		intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,  in vlv_initial_power_sequencer_setup()
302 	if (intel_dp->pps.pps_pipe == INVALID_PIPE) {  in vlv_initial_power_sequencer_setup()
314 		    pipe_name(intel_dp->pps.pps_pipe));  in vlv_initial_power_sequencer_setup()
341 			    intel_dp->pps.active_pipe != INVALID_PIPE);  in intel_pps_reset_all()
347 			intel_dp->pps.pps_reset = true;  in intel_pps_reset_all()
349 			intel_dp->pps.pps_pipe = INVALID_PIPE;  in intel_pps_reset_all()
411 	lockdep_assert_held(&dev_priv->display.pps.mutex);  in edp_have_panel_power()
414 	    intel_dp->pps.pps_pipe == INVALID_PIPE)  in edp_have_panel_power()
424 	lockdep_assert_held(&dev_priv->display.pps.mutex);  in edp_have_panel_vdd()
427 	    intel_dp->pps.pps_pipe == INVALID_PIPE)  in edp_have_panel_vdd()
467 	lockdep_assert_held(&dev_priv->display.pps.mutex);  in wait_panel_status()
517 	panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time);  in wait_panel_power_cycle()
521 	if (panel_power_off_duration < (s64)intel_dp->pps.panel_power_cycle_delay)  in wait_panel_power_cycle()
523 				       intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration);  in wait_panel_power_cycle()
541 	wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on,  in wait_backlight_on()
542 				       intel_dp->pps.backlight_on_delay);  in wait_backlight_on()
547 	wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off,  in edp_wait_backlight_off()
548 				       intel_dp->pps.backlight_off_delay);  in edp_wait_backlight_off()
560 	lockdep_assert_held(&dev_priv->display.pps.mutex);  in ilk_get_pp_control()
582 	bool need_to_disable = !intel_dp->pps.want_panel_vdd;  in intel_pps_vdd_on_unlocked()
584 	lockdep_assert_held(&dev_priv->display.pps.mutex);  in intel_pps_vdd_on_unlocked()
589 	cancel_delayed_work(&intel_dp->pps.panel_vdd_work);  in intel_pps_vdd_on_unlocked()
590 	intel_dp->pps.want_panel_vdd = true;  in intel_pps_vdd_on_unlocked()
595 	drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref);  in intel_pps_vdd_on_unlocked()
596 	intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,  in intel_pps_vdd_on_unlocked()
625 		msleep(intel_dp->pps.panel_power_up_delay);  in intel_pps_vdd_on_unlocked()
661 	lockdep_assert_held(&dev_priv->display.pps.mutex);  in intel_pps_vdd_off_sync_unlocked()
663 	drm_WARN_ON(&dev_priv->drm, intel_dp->pps.want_panel_vdd);  in intel_pps_vdd_off_sync_unlocked()
687 		intel_dp->pps.panel_power_off_time = ktime_get_boottime();  in intel_pps_vdd_off_sync_unlocked()
691 				fetch_and_zero(&intel_dp->pps.vdd_wakeref));  in intel_pps_vdd_off_sync_unlocked()
701 	cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work);  in intel_pps_vdd_off_sync()
712 	struct intel_pps *pps = container_of(to_delayed_work(__work),  in edp_panel_vdd_work()  local
714 	struct intel_dp *intel_dp = container_of(pps, struct intel_dp, pps);  in edp_panel_vdd_work()
718 		if (!intel_dp->pps.want_panel_vdd)  in edp_panel_vdd_work()
731 	if (intel_dp->pps.initializing)  in edp_panel_vdd_schedule_off()
739 	delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5);  in edp_panel_vdd_schedule_off()
740 	schedule_delayed_work(&intel_dp->pps.panel_vdd_work, delay);  in edp_panel_vdd_schedule_off()
752 	lockdep_assert_held(&dev_priv->display.pps.mutex);  in intel_pps_vdd_off_unlocked()
757 	I915_STATE_WARN(!intel_dp->pps.want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",  in intel_pps_vdd_off_unlocked()
761 	intel_dp->pps.want_panel_vdd = false;  in intel_pps_vdd_off_unlocked()
775 	lockdep_assert_held(&dev_priv->display.pps.mutex);  in intel_pps_on_unlocked()
809 	intel_dp->pps.last_power_on = jiffies;  in intel_pps_on_unlocked()
836 	lockdep_assert_held(&dev_priv->display.pps.mutex);  in intel_pps_off_unlocked()
844 	drm_WARN(&dev_priv->drm, !intel_dp->pps.want_panel_vdd,  in intel_pps_off_unlocked()
856 	intel_dp->pps.want_panel_vdd = false;  in intel_pps_off_unlocked()
862 	intel_dp->pps.panel_power_off_time = ktime_get_boottime();  in intel_pps_off_unlocked()
867 				fetch_and_zero(&intel_dp->pps.vdd_wakeref));  in intel_pps_off_unlocked()
927 	intel_dp->pps.last_backlight_off = jiffies;  in intel_pps_backlight_off()
961 	enum pipe pipe = intel_dp->pps.pps_pipe;  in vlv_detach_power_sequencer()
964 	drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);  in vlv_detach_power_sequencer()
987 	intel_dp->pps.pps_pipe = INVALID_PIPE;  in vlv_detach_power_sequencer()
995 	lockdep_assert_held(&dev_priv->display.pps.mutex);  in vlv_steal_power_sequencer()
1000 		drm_WARN(&dev_priv->drm, intel_dp->pps.active_pipe == pipe,  in vlv_steal_power_sequencer()
1005 		if (intel_dp->pps.pps_pipe != pipe)  in vlv_steal_power_sequencer()
1025 	lockdep_assert_held(&dev_priv->display.pps.mutex);  in vlv_pps_init()
1027 	drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);  in vlv_pps_init()
1029 	if (intel_dp->pps.pps_pipe != INVALID_PIPE &&  in vlv_pps_init()
1030 	    intel_dp->pps.pps_pipe != crtc->pipe) {  in vlv_pps_init()
1045 	intel_dp->pps.active_pipe = crtc->pipe;  in vlv_pps_init()
1051 	intel_dp->pps.pps_pipe = crtc->pipe;  in vlv_pps_init()
1055 		    pipe_name(intel_dp->pps.pps_pipe), encoder->base.base.id,  in vlv_pps_init()
1068 	lockdep_assert_held(&dev_priv->display.pps.mutex);  in pps_vdd_init()
1081 	drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref);  in pps_vdd_init()
1082 	intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,  in pps_vdd_init()
1101 	intel_dp->pps.panel_power_off_time = ktime_get_boottime();  in pps_init_timestamps()
1102 	intel_dp->pps.last_power_on = jiffies;  in pps_init_timestamps()
1103 	intel_dp->pps.last_backlight_off = jiffies;  in pps_init_timestamps()
1117 	/* Ensure PPS is unlocked */  in intel_pps_readout_hw_state()
1157 	struct edp_power_seq *sw = &intel_dp->pps.pps_delays;  in intel_pps_verify_state()
1163 		drm_err(&i915->drm, "PPS state mismatch\n");  in intel_pps_verify_state()
1180 	lockdep_assert_held(&dev_priv->display.pps.mutex);  in pps_init_delays_bios()
1182 	if (!pps_delays_valid(&intel_dp->pps.bios_pps_delays))  in pps_init_delays_bios()
1183 		intel_pps_readout_hw_state(intel_dp, &intel_dp->pps.bios_pps_delays);  in pps_init_delays_bios()
1185 	*bios = intel_dp->pps.bios_pps_delays;  in pps_init_delays_bios()
1196 	*vbt = connector->panel.vbt.edp.pps;  in pps_init_delays_vbt()
1227 	lockdep_assert_held(&dev_priv->display.pps.mutex);  in pps_init_delays_spec()
1248 		*final = &intel_dp->pps.pps_delays;  in pps_init_delays()
1250 	lockdep_assert_held(&dev_priv->display.pps.mutex);  in pps_init_delays()
1273 	intel_dp->pps.panel_power_up_delay = get_delay(t1_t3);  in pps_init_delays()
1274 	intel_dp->pps.backlight_on_delay = get_delay(t8);  in pps_init_delays()
1275 	intel_dp->pps.backlight_off_delay = get_delay(t9);  in pps_init_delays()
1276 	intel_dp->pps.panel_power_down_delay = get_delay(t10);  in pps_init_delays()
1277 	intel_dp->pps.panel_power_cycle_delay = get_delay(t11_t12);  in pps_init_delays()
1282 		    intel_dp->pps.panel_power_up_delay,  in pps_init_delays()
1283 		    intel_dp->pps.panel_power_down_delay,  in pps_init_delays()
1284 		    intel_dp->pps.panel_power_cycle_delay);  in pps_init_delays()
1287 		    intel_dp->pps.backlight_on_delay,  in pps_init_delays()
1288 		    intel_dp->pps.backlight_off_delay);  in pps_init_delays()
1314 	const struct edp_power_seq *seq = &intel_dp->pps.pps_delays;  in pps_init_registers()
1316 	lockdep_assert_held(&dev_priv->display.pps.mutex);  in pps_init_registers()
1432 	intel_dp->pps.initializing = true;  in intel_pps_init()
1433 	INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);  in intel_pps_init()
1453 		memset(&intel_dp->pps.pps_delays, 0, sizeof(intel_dp->pps.pps_delays));  in intel_pps_init_late()
1457 		intel_dp->pps.initializing = false;  in intel_pps_init_late()
1491 		i915->display.pps.mmio_base = PCH_PPS_BASE;  in intel_pps_setup()
1493 		i915->display.pps.mmio_base = VLV_PPS_BASE;  in intel_pps_setup()
1495 		i915->display.pps.mmio_base = PPS_BASE;  in intel_pps_setup()