158 					struct intel_lvds_pps *pps)  in intel_lvds_pps_get_hw_state()  argument
162 	pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET;  in intel_lvds_pps_get_hw_state()
165 	pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val);  in intel_lvds_pps_get_hw_state()
166 	pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val);  in intel_lvds_pps_get_hw_state()
167 	pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val);  in intel_lvds_pps_get_hw_state()
170 	pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val);  in intel_lvds_pps_get_hw_state()
171 	pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val);  in intel_lvds_pps_get_hw_state()
174 	pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);  in intel_lvds_pps_get_hw_state()
184 	pps->t4 = val * 1000;  in intel_lvds_pps_get_hw_state()
187 	    pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {  in intel_lvds_pps_get_hw_state()
192 		pps->t1_t2 = 40 * 10;  in intel_lvds_pps_get_hw_state()
193 		pps->t5 = 200 * 10;  in intel_lvds_pps_get_hw_state()
195 		pps->t3 = 35 * 10;  in intel_lvds_pps_get_hw_state()
196 		pps->tx = 200 * 10;  in intel_lvds_pps_get_hw_state()
201 		pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,  in intel_lvds_pps_get_hw_state()
202 		pps->divider, pps->port, pps->powerdown_on_reset);  in intel_lvds_pps_get_hw_state()
206 				   struct intel_lvds_pps *pps)  in intel_lvds_pps_init_hw()  argument
213 	if (pps->powerdown_on_reset)  in intel_lvds_pps_init_hw()
218 …_PORT_SELECT_MASK, pps->port) | REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | REG_FIELD_…  in intel_lvds_pps_init_hw()
221 …REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, …  in intel_lvds_pps_init_hw()
224 …FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK,…  in intel_lvds_pps_init_hw()