Lines Matching +full:db4 +full:- +full:db7
3 * Copyright © 2006-2009 Intel Corporation
61 return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev); in intel_hdmi_to_i915()
72 drm_WARN(&dev_priv->drm, in assert_hdmi_port_disabled()
73 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, in assert_hdmi_port_disabled()
81 drm_WARN(&dev_priv->drm, in assert_hdmi_transcoder_func_disabled()
203 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in g4x_write_infoframe()
207 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), in g4x_write_infoframe()
238 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in g4x_read_infoframe()
256 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in g4x_infoframes_enabled()
262 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) in g4x_infoframes_enabled()
275 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in ibx_write_infoframe()
276 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ibx_write_infoframe()
277 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); in ibx_write_infoframe()
281 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), in ibx_write_infoframe()
292 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), in ibx_write_infoframe()
298 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0); in ibx_write_infoframe()
313 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in ibx_read_infoframe()
314 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ibx_read_infoframe()
318 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); in ibx_read_infoframe()
323 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); in ibx_read_infoframe()
326 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); in ibx_read_infoframe()
332 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in ibx_infoframes_enabled()
333 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; in ibx_infoframes_enabled()
340 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) in ibx_infoframes_enabled()
354 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in cpt_write_infoframe()
355 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in cpt_write_infoframe()
356 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); in cpt_write_infoframe()
360 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), in cpt_write_infoframe()
374 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), in cpt_write_infoframe()
380 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0); in cpt_write_infoframe()
395 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in cpt_read_infoframe()
396 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in cpt_read_infoframe()
400 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); in cpt_read_infoframe()
405 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); in cpt_read_infoframe()
408 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); in cpt_read_infoframe()
414 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in cpt_infoframes_enabled()
415 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; in cpt_infoframes_enabled()
432 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_write_infoframe()
433 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_write_infoframe()
434 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); in vlv_write_infoframe()
438 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), in vlv_write_infoframe()
450 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data); in vlv_write_infoframe()
456 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0); in vlv_write_infoframe()
471 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_read_infoframe()
472 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_read_infoframe()
476 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe)); in vlv_read_infoframe()
481 intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val); in vlv_read_infoframe()
485 VLV_TVIDEO_DIP_DATA(crtc->pipe)); in vlv_read_infoframe()
491 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_infoframes_enabled()
492 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; in vlv_infoframes_enabled()
498 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) in vlv_infoframes_enabled()
512 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_write_infoframe()
513 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in hsw_write_infoframe()
521 drm_WARN_ON(&dev_priv->drm, len > data_size); in hsw_write_infoframe()
539 if (DISPLAY_VER(dev_priv) == 13 && crtc_state->has_psr && in hsw_write_infoframe()
552 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_read_infoframe()
553 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in hsw_read_infoframe()
565 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_infoframes_enabled()
567 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); in hsw_infoframes_enabled()
605 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_infoframes_enabled()
610 val = dig_port->infoframes_enabled(encoder, crtc_state); in intel_hdmi_infoframes_enabled()
636 * DW2: DB7 | DB6 | DB5 | DB4
654 if ((crtc_state->infoframes.enable & in intel_write_infoframe()
658 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) in intel_write_infoframe()
662 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); in intel_write_infoframe()
663 if (drm_WARN_ON(encoder->base.dev, len < 0)) in intel_write_infoframe()
671 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); in intel_write_infoframe()
683 if ((crtc_state->infoframes.enable & in intel_read_infoframe()
687 dig_port->read_infoframe(encoder, crtc_state, in intel_read_infoframe()
694 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); in intel_read_infoframe()
696 drm_dbg_kms(encoder->base.dev, in intel_read_infoframe()
701 if (frame->any.type != type) in intel_read_infoframe()
702 drm_dbg_kms(encoder->base.dev, in intel_read_infoframe()
704 frame->any.type, type); in intel_read_infoframe()
712 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; in intel_hdmi_compute_avi_infoframe()
714 &crtc_state->hw.adjusted_mode; in intel_hdmi_compute_avi_infoframe()
715 struct drm_connector *connector = conn_state->connector; in intel_hdmi_compute_avi_infoframe()
718 if (!crtc_state->has_infoframe) in intel_hdmi_compute_avi_infoframe()
721 crtc_state->infoframes.enable |= in intel_hdmi_compute_avi_infoframe()
729 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) in intel_hdmi_compute_avi_infoframe()
730 frame->colorspace = HDMI_COLORSPACE_YUV420; in intel_hdmi_compute_avi_infoframe()
731 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) in intel_hdmi_compute_avi_infoframe()
732 frame->colorspace = HDMI_COLORSPACE_YUV444; in intel_hdmi_compute_avi_infoframe()
734 frame->colorspace = HDMI_COLORSPACE_RGB; in intel_hdmi_compute_avi_infoframe()
739 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && in intel_hdmi_compute_avi_infoframe()
740 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); in intel_hdmi_compute_avi_infoframe()
742 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { in intel_hdmi_compute_avi_infoframe()
745 crtc_state->limited_color_range ? in intel_hdmi_compute_avi_infoframe()
749 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; in intel_hdmi_compute_avi_infoframe()
750 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; in intel_hdmi_compute_avi_infoframe()
758 if (drm_WARN_ON(encoder->base.dev, ret)) in intel_hdmi_compute_avi_infoframe()
769 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; in intel_hdmi_compute_spd_infoframe()
772 if (!crtc_state->has_infoframe) in intel_hdmi_compute_spd_infoframe()
775 crtc_state->infoframes.enable |= in intel_hdmi_compute_spd_infoframe()
779 if (drm_WARN_ON(encoder->base.dev, ret)) in intel_hdmi_compute_spd_infoframe()
782 frame->sdi = HDMI_SPD_SDI_PC; in intel_hdmi_compute_spd_infoframe()
785 if (drm_WARN_ON(encoder->base.dev, ret)) in intel_hdmi_compute_spd_infoframe()
797 &crtc_state->infoframes.hdmi.vendor.hdmi; in intel_hdmi_compute_hdmi_infoframe()
799 &conn_state->connector->display_info; in intel_hdmi_compute_hdmi_infoframe()
802 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) in intel_hdmi_compute_hdmi_infoframe()
805 crtc_state->infoframes.enable |= in intel_hdmi_compute_hdmi_infoframe()
809 conn_state->connector, in intel_hdmi_compute_hdmi_infoframe()
810 &crtc_state->hw.adjusted_mode); in intel_hdmi_compute_hdmi_infoframe()
811 if (drm_WARN_ON(encoder->base.dev, ret)) in intel_hdmi_compute_hdmi_infoframe()
815 if (drm_WARN_ON(encoder->base.dev, ret)) in intel_hdmi_compute_hdmi_infoframe()
826 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; in intel_hdmi_compute_drm_infoframe()
827 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_compute_drm_infoframe()
833 if (!crtc_state->has_infoframe) in intel_hdmi_compute_drm_infoframe()
836 if (!conn_state->hdr_output_metadata) in intel_hdmi_compute_drm_infoframe()
839 crtc_state->infoframes.enable |= in intel_hdmi_compute_drm_infoframe()
844 drm_dbg_kms(&dev_priv->drm, in intel_hdmi_compute_drm_infoframe()
850 if (drm_WARN_ON(&dev_priv->drm, ret)) in intel_hdmi_compute_drm_infoframe()
861 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in g4x_set_infoframes()
863 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; in g4x_set_infoframes()
866 u32 port = VIDEO_DIP_PORT(encoder->port); in g4x_set_infoframes()
885 drm_dbg_kms(&dev_priv->drm, in g4x_set_infoframes()
899 drm_dbg_kms(&dev_priv->drm, in g4x_set_infoframes()
917 &crtc_state->infoframes.avi); in g4x_set_infoframes()
920 &crtc_state->infoframes.spd); in g4x_set_infoframes()
923 &crtc_state->infoframes.hdmi); in g4x_set_infoframes()
930 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
931 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
932 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
933 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
959 return mode->crtc_hdisplay % pixels_per_group == 0 && in gcp_default_phase_possible()
960 mode->crtc_htotal % pixels_per_group == 0 && in gcp_default_phase_possible()
961 mode->crtc_hblank_start % pixels_per_group == 0 && in gcp_default_phase_possible()
962 mode->crtc_hblank_end % pixels_per_group == 0 && in gcp_default_phase_possible()
963 mode->crtc_hsync_start % pixels_per_group == 0 && in gcp_default_phase_possible()
964 mode->crtc_hsync_end % pixels_per_group == 0 && in gcp_default_phase_possible()
965 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || in gcp_default_phase_possible()
966 mode->crtc_htotal/2 % pixels_per_group == 0); in gcp_default_phase_possible()
973 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_set_gcp_infoframe()
974 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_hdmi_set_gcp_infoframe()
977 if ((crtc_state->infoframes.enable & in intel_hdmi_set_gcp_infoframe()
982 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); in intel_hdmi_set_gcp_infoframe()
984 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); in intel_hdmi_set_gcp_infoframe()
986 reg = TVIDEO_DIP_GCP(crtc->pipe); in intel_hdmi_set_gcp_infoframe()
990 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp); in intel_hdmi_set_gcp_infoframe()
998 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_read_gcp_infoframe()
999 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_hdmi_read_gcp_infoframe()
1002 if ((crtc_state->infoframes.enable & in intel_hdmi_read_gcp_infoframe()
1007 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); in intel_hdmi_read_gcp_infoframe()
1009 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); in intel_hdmi_read_gcp_infoframe()
1011 reg = TVIDEO_DIP_GCP(crtc->pipe); in intel_hdmi_read_gcp_infoframe()
1015 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg); in intel_hdmi_read_gcp_infoframe()
1022 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_compute_gcp_infoframe()
1024 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) in intel_hdmi_compute_gcp_infoframe()
1027 crtc_state->infoframes.enable |= in intel_hdmi_compute_gcp_infoframe()
1031 if (crtc_state->pipe_bpp > 24) in intel_hdmi_compute_gcp_infoframe()
1032 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; in intel_hdmi_compute_gcp_infoframe()
1035 if (gcp_default_phase_possible(crtc_state->pipe_bpp, in intel_hdmi_compute_gcp_infoframe()
1036 &crtc_state->hw.adjusted_mode)) in intel_hdmi_compute_gcp_infoframe()
1037 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; in intel_hdmi_compute_gcp_infoframe()
1045 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in ibx_set_infoframes()
1046 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ibx_set_infoframes()
1048 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; in ibx_set_infoframes()
1049 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); in ibx_set_infoframes()
1051 u32 port = VIDEO_DIP_PORT(encoder->port); in ibx_set_infoframes()
1070 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, in ibx_set_infoframes()
1090 &crtc_state->infoframes.avi); in ibx_set_infoframes()
1093 &crtc_state->infoframes.spd); in ibx_set_infoframes()
1096 &crtc_state->infoframes.hdmi); in ibx_set_infoframes()
1104 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in cpt_set_infoframes()
1105 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in cpt_set_infoframes()
1107 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); in cpt_set_infoframes()
1139 &crtc_state->infoframes.avi); in cpt_set_infoframes()
1142 &crtc_state->infoframes.spd); in cpt_set_infoframes()
1145 &crtc_state->infoframes.hdmi); in cpt_set_infoframes()
1153 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_set_infoframes()
1154 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_set_infoframes()
1156 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); in vlv_set_infoframes()
1158 u32 port = VIDEO_DIP_PORT(encoder->port); in vlv_set_infoframes()
1177 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, in vlv_set_infoframes()
1197 &crtc_state->infoframes.avi); in vlv_set_infoframes()
1200 &crtc_state->infoframes.spd); in vlv_set_infoframes()
1203 &crtc_state->infoframes.hdmi); in vlv_set_infoframes()
1211 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_set_infoframes()
1212 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); in hsw_set_infoframes()
1216 crtc_state->cpu_transcoder); in hsw_set_infoframes()
1237 &crtc_state->infoframes.avi); in hsw_set_infoframes()
1240 &crtc_state->infoframes.spd); in hsw_set_infoframes()
1243 &crtc_state->infoframes.hdmi); in hsw_set_infoframes()
1246 &crtc_state->infoframes.drm); in hsw_set_infoframes()
1254 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) in intel_dp_dual_mode_set_tmds_output()
1257 adapter = intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); in intel_dp_dual_mode_set_tmds_output()
1259 drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n", in intel_dp_dual_mode_set_tmds_output()
1262 drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, hdmi->dp_dual_mode.type, adapter, enable); in intel_dp_dual_mode_set_tmds_output()
1268 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp_read()
1269 struct intel_hdmi *hdmi = &dig_port->hdmi; in intel_hdmi_hdcp_read()
1271 hdmi->ddc_bus); in intel_hdmi_hdcp_read()
1291 return ret >= 0 ? -EIO : ret; in intel_hdmi_hdcp_read()
1297 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp_write()
1298 struct intel_hdmi *hdmi = &dig_port->hdmi; in intel_hdmi_hdcp_write()
1300 hdmi->ddc_bus); in intel_hdmi_hdcp_write()
1307 return -ENOMEM; in intel_hdmi_hdcp_write()
1321 ret = -EIO; in intel_hdmi_hdcp_write()
1331 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp_write_an_aksv()
1332 struct intel_hdmi *hdmi = &dig_port->hdmi; in intel_hdmi_hdcp_write_an_aksv()
1334 hdmi->ddc_bus); in intel_hdmi_hdcp_write_an_aksv()
1340 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n", in intel_hdmi_hdcp_write_an_aksv()
1347 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret); in intel_hdmi_hdcp_write_an_aksv()
1356 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp_read_bksv()
1362 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n", in intel_hdmi_hdcp_read_bksv()
1371 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp_read_bstatus()
1377 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n", in intel_hdmi_hdcp_read_bstatus()
1386 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp_repeater_present()
1392 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", in intel_hdmi_hdcp_repeater_present()
1404 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp_read_ri_prime()
1410 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n", in intel_hdmi_hdcp_read_ri_prime()
1419 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp_read_ksv_ready()
1425 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", in intel_hdmi_hdcp_read_ksv_ready()
1437 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp_read_ksv_fifo()
1442 drm_dbg_kms(&i915->drm, in intel_hdmi_hdcp_read_ksv_fifo()
1453 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp_read_v_prime_part()
1457 return -EINVAL; in intel_hdmi_hdcp_read_v_prime_part()
1462 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n", in intel_hdmi_hdcp_read_v_prime_part()
1470 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); in kbl_repositioning_enc_en_signal()
1472 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc); in kbl_repositioning_enc_en_signal()
1477 scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe)); in kbl_repositioning_enc_en_signal()
1483 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, in kbl_repositioning_enc_en_signal()
1486 drm_err(&dev_priv->drm, in kbl_repositioning_enc_en_signal()
1491 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, in kbl_repositioning_enc_en_signal()
1494 drm_err(&dev_priv->drm, in kbl_repositioning_enc_en_signal()
1507 struct intel_hdmi *hdmi = &dig_port->hdmi; in intel_hdmi_hdcp_toggle_signalling()
1508 struct intel_connector *connector = hdmi->attached_connector; in intel_hdmi_hdcp_toggle_signalling()
1509 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); in intel_hdmi_hdcp_toggle_signalling()
1515 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, in intel_hdmi_hdcp_toggle_signalling()
1519 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n", in intel_hdmi_hdcp_toggle_signalling()
1539 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp_check_link_once()
1540 enum port port = dig_port->base.port; in intel_hdmi_hdcp_check_link_once()
1541 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; in intel_hdmi_hdcp_check_link_once()
1558 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n", in intel_hdmi_hdcp_check_link_once()
1570 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp_check_link()
1577 drm_err(&i915->drm, "Link check failed\n"); in intel_hdmi_hdcp_check_link()
1620 return -EINVAL; in get_hdcp2_msg_timeout()
1628 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in hdcp2_detect_msg_availability()
1634 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n", in hdcp2_detect_msg_availability()
1655 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp2_wait_for_msg()
1670 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n", in intel_hdmi_hdcp2_wait_for_msg()
1690 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp2_read_msg()
1691 struct intel_hdmi *hdmi = &dig_port->hdmi; in intel_hdmi_hdcp2_read_msg()
1692 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; in intel_hdmi_hdcp2_read_msg()
1697 hdcp->is_paired); in intel_hdmi_hdcp2_read_msg()
1706 drm_dbg_kms(&i915->drm, in intel_hdmi_hdcp2_read_msg()
1709 return -EINVAL; in intel_hdmi_hdcp2_read_msg()
1715 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n", in intel_hdmi_hdcp2_read_msg()
1733 * Re-auth request and Link Integrity Failures are represented by in intel_hdmi_hdcp2_check_link()
1780 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_source_max_tmds_clock()
1802 return hdmi->has_hdmi_sink && in intel_has_hdmi_sink()
1803 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; in intel_has_hdmi_sink()
1808 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420; in intel_hdmi_is_ycbcr420()
1815 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; in hdmi_port_clock_limit()
1819 struct intel_connector *connector = hdmi->attached_connector; in hdmi_port_clock_limit()
1820 const struct drm_display_info *info = &connector->base.display_info; in hdmi_port_clock_limit()
1822 if (hdmi->dp_dual_mode.max_tmds_clock) in hdmi_port_clock_limit()
1824 hdmi->dp_dual_mode.max_tmds_clock); in hdmi_port_clock_limit()
1826 if (info->max_tmds_clock) in hdmi_port_clock_limit()
1828 info->max_tmds_clock); in hdmi_port_clock_limit()
1842 enum phy phy = intel_port_to_phy(dev_priv, hdmi_to_dig_port(hdmi)->base.port); in hdmi_port_clock_valid()
1850 /* GLK DPLL can't generate 446-480 MHz */ in hdmi_port_clock_valid()
1854 /* BXT/GLK DPLL can't generate 223-240 MHz */ in hdmi_port_clock_valid()
1859 /* CHV DPLL can't generate 216-240 MHz */ in hdmi_port_clock_valid()
1863 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */ in hdmi_port_clock_valid()
1867 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */ in hdmi_port_clock_valid()
1872 * SNPS PHYs' MPLLB table-based programming can only handle a fixed in hdmi_port_clock_valid()
1916 const struct drm_display_info *info = &connector->display_info; in intel_hdmi_sink_bpc_possible()
1917 const struct drm_hdmi_info *hdmi = &info->hdmi; in intel_hdmi_sink_bpc_possible()
1925 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36; in intel_hdmi_sink_bpc_possible()
1927 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36; in intel_hdmi_sink_bpc_possible()
1933 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30; in intel_hdmi_sink_bpc_possible()
1935 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30; in intel_hdmi_sink_bpc_possible()
1948 struct drm_i915_private *i915 = to_i915(connector->dev); in intel_hdmi_mode_clock_valid()
1958 for (bpc = 12; bpc >= 8; bpc -= 2) { in intel_hdmi_mode_clock_valid()
1973 drm_WARN_ON(&i915->drm, status == MODE_OK); in intel_hdmi_mode_clock_valid()
1985 int clock = mode->clock; in intel_hdmi_mode_valid()
1986 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; in intel_hdmi_mode_valid()
1987 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); in intel_hdmi_mode_valid()
1990 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) in intel_hdmi_mode_valid()
1993 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) in intel_hdmi_mode_valid()
1999 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { in intel_hdmi_mode_valid()
2014 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode); in intel_hdmi_mode_valid()
2019 !connector->ycbcr_420_allowed || in intel_hdmi_mode_valid()
2020 !drm_mode_is_420_also(&connector->display_info, mode)) in intel_hdmi_mode_valid()
2034 struct drm_atomic_state *state = crtc_state->uapi.state; in intel_hdmi_bpc_possible()
2040 if (connector_state->crtc != crtc_state->uapi.crtc) in intel_hdmi_bpc_possible()
2053 to_i915(crtc_state->uapi.crtc->dev); in hdmi_bpc_possible()
2055 &crtc_state->hw.adjusted_mode; in hdmi_bpc_possible()
2064 if (bpc > 8 && crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI)) in hdmi_bpc_possible()
2070 (adjusted_mode->crtc_hblank_end - in hdmi_bpc_possible()
2071 adjusted_mode->crtc_hblank_start) % 8 == 2) in hdmi_bpc_possible()
2074 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink, in hdmi_bpc_possible()
2090 bpc = max(crtc_state->pipe_bpp / 3, 8); in intel_hdmi_compute_bpc()
2100 for (; bpc >= 8; bpc -= 2) { in intel_hdmi_compute_bpc()
2106 crtc_state->has_hdmi_sink) == MODE_OK) in intel_hdmi_compute_bpc()
2110 return -EINVAL; in intel_hdmi_compute_bpc()
2117 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_hdmi_compute_clock()
2119 &crtc_state->hw.adjusted_mode; in intel_hdmi_compute_clock()
2120 int bpc, clock = adjusted_mode->crtc_clock; in intel_hdmi_compute_clock()
2122 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) in intel_hdmi_compute_clock()
2130 crtc_state->port_clock = in intel_hdmi_compute_clock()
2138 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); in intel_hdmi_compute_clock()
2140 drm_dbg_kms(&i915->drm, in intel_hdmi_compute_clock()
2142 bpc, crtc_state->pipe_bpp); in intel_hdmi_compute_clock()
2153 &crtc_state->hw.adjusted_mode; in intel_hdmi_limited_color_range()
2157 * crtc_state->limited_color_range only applies to RGB, in intel_hdmi_limited_color_range()
2162 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) in intel_hdmi_limited_color_range()
2165 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { in intel_hdmi_limited_color_range()
2166 /* See CEA-861-E - 5.1 Default Encoding Parameters */ in intel_hdmi_limited_color_range()
2167 return crtc_state->has_hdmi_sink && in intel_hdmi_limited_color_range()
2171 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; in intel_hdmi_limited_color_range()
2183 if (!crtc_state->has_hdmi_sink) in intel_hdmi_has_audio()
2186 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) in intel_hdmi_has_audio()
2187 return intel_hdmi->has_audio; in intel_hdmi_has_audio()
2189 return intel_conn_state->force_audio == HDMI_AUDIO_ON; in intel_hdmi_has_audio()
2196 if (connector->base.ycbcr_420_allowed && ycbcr_420_output) in intel_hdmi_output_format()
2207 struct intel_connector *connector = to_intel_connector(conn_state->connector); in intel_hdmi_compute_output_format()
2208 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_hdmi_compute_output_format()
2209 const struct drm_display_info *info = &connector->base.display_info; in intel_hdmi_compute_output_format()
2210 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_hdmi_compute_output_format()
2214 crtc_state->output_format = intel_hdmi_output_format(connector, ycbcr_420_only); in intel_hdmi_compute_output_format()
2217 drm_dbg_kms(&i915->drm, in intel_hdmi_compute_output_format()
2219 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_hdmi_compute_output_format()
2225 !connector->base.ycbcr_420_allowed || in intel_hdmi_compute_output_format()
2229 crtc_state->output_format = intel_hdmi_output_format(connector, true); in intel_hdmi_compute_output_format()
2241 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_compute_config()
2242 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_hdmi_compute_config()
2243 struct drm_connector *connector = conn_state->connector; in intel_hdmi_compute_config()
2244 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; in intel_hdmi_compute_config()
2247 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in intel_hdmi_compute_config()
2248 return -EINVAL; in intel_hdmi_compute_config()
2250 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_hdmi_compute_config()
2251 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi, in intel_hdmi_compute_config()
2254 if (pipe_config->has_hdmi_sink) in intel_hdmi_compute_config()
2255 pipe_config->has_infoframe = true; in intel_hdmi_compute_config()
2257 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) in intel_hdmi_compute_config()
2258 pipe_config->pixel_multiplier = 2; in intel_hdmi_compute_config()
2261 pipe_config->has_pch_encoder = true; in intel_hdmi_compute_config()
2263 pipe_config->has_audio = in intel_hdmi_compute_config()
2274 drm_dbg_kms(&dev_priv->drm, in intel_hdmi_compute_config()
2276 pipe_config->hw.adjusted_mode.crtc_clock); in intel_hdmi_compute_config()
2286 pipe_config->limited_color_range = in intel_hdmi_compute_config()
2289 if (conn_state->picture_aspect_ratio) in intel_hdmi_compute_config()
2290 adjusted_mode->picture_aspect_ratio = in intel_hdmi_compute_config()
2291 conn_state->picture_aspect_ratio; in intel_hdmi_compute_config()
2293 pipe_config->lane_count = 4; in intel_hdmi_compute_config()
2295 if (scdc->scrambling.supported && DISPLAY_VER(dev_priv) >= 10) { in intel_hdmi_compute_config()
2296 if (scdc->scrambling.low_rates) in intel_hdmi_compute_config()
2297 pipe_config->hdmi_scrambling = true; in intel_hdmi_compute_config()
2299 if (pipe_config->port_clock > 340000) { in intel_hdmi_compute_config()
2300 pipe_config->hdmi_scrambling = true; in intel_hdmi_compute_config()
2301 pipe_config->hdmi_high_tmds_clock_ratio = true; in intel_hdmi_compute_config()
2309 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n"); in intel_hdmi_compute_config()
2310 return -EINVAL; in intel_hdmi_compute_config()
2314 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n"); in intel_hdmi_compute_config()
2315 return -EINVAL; in intel_hdmi_compute_config()
2319 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n"); in intel_hdmi_compute_config()
2320 return -EINVAL; in intel_hdmi_compute_config()
2324 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n"); in intel_hdmi_compute_config()
2325 return -EINVAL; in intel_hdmi_compute_config()
2347 intel_hdmi->has_hdmi_sink = false; in intel_hdmi_unset_edid()
2348 intel_hdmi->has_audio = false; in intel_hdmi_unset_edid()
2350 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; in intel_hdmi_unset_edid()
2351 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; in intel_hdmi_unset_edid()
2353 kfree(to_intel_connector(connector)->detect_edid); in intel_hdmi_unset_edid()
2354 to_intel_connector(connector)->detect_edid = NULL; in intel_hdmi_unset_edid()
2360 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_hdmi_dp_dual_mode_detect()
2362 enum port port = hdmi_to_dig_port(hdmi)->base.port; in intel_hdmi_dp_dual_mode_detect()
2364 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); in intel_hdmi_dp_dual_mode_detect()
2365 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(&dev_priv->drm, adapter); in intel_hdmi_dp_dual_mode_detect()
2383 if (has_edid && !connector->override_edid && in intel_hdmi_dp_dual_mode_detect()
2385 drm_dbg_kms(&dev_priv->drm, in intel_hdmi_dp_dual_mode_detect()
2396 hdmi->dp_dual_mode.type = type; in intel_hdmi_dp_dual_mode_detect()
2397 hdmi->dp_dual_mode.max_tmds_clock = in intel_hdmi_dp_dual_mode_detect()
2398 drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, adapter); in intel_hdmi_dp_dual_mode_detect()
2400 drm_dbg_kms(&dev_priv->drm, in intel_hdmi_dp_dual_mode_detect()
2403 hdmi->dp_dual_mode.max_tmds_clock); in intel_hdmi_dp_dual_mode_detect()
2408 drm_dbg_kms(&dev_priv->drm, in intel_hdmi_dp_dual_mode_detect()
2410 hdmi->dp_dual_mode.max_tmds_clock = 0; in intel_hdmi_dp_dual_mode_detect()
2417 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_hdmi_set_edid()
2426 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); in intel_hdmi_set_edid()
2431 drm_dbg_kms(&dev_priv->drm, in intel_hdmi_set_edid()
2432 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); in intel_hdmi_set_edid()
2442 to_intel_connector(connector)->detect_edid = edid; in intel_hdmi_set_edid()
2443 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { in intel_hdmi_set_edid()
2444 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); in intel_hdmi_set_edid()
2445 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); in intel_hdmi_set_edid()
2450 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid); in intel_hdmi_set_edid()
2459 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_hdmi_detect()
2461 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; in intel_hdmi_detect()
2464 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", in intel_hdmi_detect()
2465 connector->base.id, connector->name); in intel_hdmi_detect()
2485 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); in intel_hdmi_detect()
2499 struct drm_i915_private *i915 = to_i915(connector->dev); in intel_hdmi_force()
2501 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", in intel_hdmi_force()
2502 connector->base.id, connector->name); in intel_hdmi_force()
2506 if (connector->status != connector_status_connected) in intel_hdmi_force()
2516 edid = to_intel_connector(connector)->detect_edid; in intel_hdmi_get_modes()
2526 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_hdmi_get_i2c_adapter()
2529 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); in intel_hdmi_get_i2c_adapter()
2534 struct drm_i915_private *i915 = to_i915(connector->dev); in intel_hdmi_create_i2c_symlink()
2536 struct kobject *i2c_kobj = &adapter->dev.kobj; in intel_hdmi_create_i2c_symlink()
2537 struct kobject *connector_kobj = &connector->kdev->kobj; in intel_hdmi_create_i2c_symlink()
2540 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name); in intel_hdmi_create_i2c_symlink()
2542 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret); in intel_hdmi_create_i2c_symlink()
2548 struct kobject *i2c_kobj = &adapter->dev.kobj; in intel_hdmi_remove_i2c_symlink()
2549 struct kobject *connector_kobj = &connector->kdev->kobj; in intel_hdmi_remove_i2c_symlink()
2551 sysfs_remove_link(connector_kobj, i2c_kobj->name); in intel_hdmi_remove_i2c_symlink()
2570 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier; in intel_hdmi_connector_unregister()
2600 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_hdmi_add_properties()
2639 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_handle_sink_scrambling()
2642 &connector->display_info.hdmi.scdc.scrambling; in intel_hdmi_handle_sink_scrambling()
2644 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); in intel_hdmi_handle_sink_scrambling()
2646 if (!sink_scrambling->supported) in intel_hdmi_handle_sink_scrambling()
2649 drm_dbg_kms(&dev_priv->drm, in intel_hdmi_handle_sink_scrambling()
2651 connector->base.id, connector->name, in intel_hdmi_handle_sink_scrambling()
2736 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port)); in icl_port_to_ddc_pin()
2771 * final two outputs use type-c pins, even though they're actually in rkl_port_to_ddc_pin()
2772 * combo outputs. With CMP, the traditional DDI A-D pins are used for in rkl_port_to_ddc_pin()
2776 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; in rkl_port_to_ddc_pin()
2785 drm_WARN_ON(&i915->drm, port == PORT_A); in gen9bc_tgp_port_to_ddc_pin()
2789 * final two outputs use type-c pins, even though they're actually in gen9bc_tgp_port_to_ddc_pin()
2790 * combo outputs. With CMP, the traditional DDI A-D pins are used for in gen9bc_tgp_port_to_ddc_pin()
2794 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; in gen9bc_tgp_port_to_ddc_pin()
2811 * Pin mapping for ADL-S requires TC pins for all combo phy outputs in adls_port_to_ddc_pin()
2817 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B; in adls_port_to_ddc_pin()
2845 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_ddc_pin()
2846 enum port port = encoder->port; in intel_hdmi_ddc_pin()
2851 drm_dbg_kms(&dev_priv->drm, in intel_hdmi_ddc_pin()
2878 drm_dbg_kms(&dev_priv->drm, in intel_hdmi_ddc_pin()
2888 to_i915(dig_port->base.base.dev); in intel_infoframe_init()
2891 dig_port->write_infoframe = vlv_write_infoframe; in intel_infoframe_init()
2892 dig_port->read_infoframe = vlv_read_infoframe; in intel_infoframe_init()
2893 dig_port->set_infoframes = vlv_set_infoframes; in intel_infoframe_init()
2894 dig_port->infoframes_enabled = vlv_infoframes_enabled; in intel_infoframe_init()
2896 dig_port->write_infoframe = g4x_write_infoframe; in intel_infoframe_init()
2897 dig_port->read_infoframe = g4x_read_infoframe; in intel_infoframe_init()
2898 dig_port->set_infoframes = g4x_set_infoframes; in intel_infoframe_init()
2899 dig_port->infoframes_enabled = g4x_infoframes_enabled; in intel_infoframe_init()
2901 if (intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) { in intel_infoframe_init()
2902 dig_port->write_infoframe = lspcon_write_infoframe; in intel_infoframe_init()
2903 dig_port->read_infoframe = lspcon_read_infoframe; in intel_infoframe_init()
2904 dig_port->set_infoframes = lspcon_set_infoframes; in intel_infoframe_init()
2905 dig_port->infoframes_enabled = lspcon_infoframes_enabled; in intel_infoframe_init()
2907 dig_port->write_infoframe = hsw_write_infoframe; in intel_infoframe_init()
2908 dig_port->read_infoframe = hsw_read_infoframe; in intel_infoframe_init()
2909 dig_port->set_infoframes = hsw_set_infoframes; in intel_infoframe_init()
2910 dig_port->infoframes_enabled = hsw_infoframes_enabled; in intel_infoframe_init()
2913 dig_port->write_infoframe = ibx_write_infoframe; in intel_infoframe_init()
2914 dig_port->read_infoframe = ibx_read_infoframe; in intel_infoframe_init()
2915 dig_port->set_infoframes = ibx_set_infoframes; in intel_infoframe_init()
2916 dig_port->infoframes_enabled = ibx_infoframes_enabled; in intel_infoframe_init()
2918 dig_port->write_infoframe = cpt_write_infoframe; in intel_infoframe_init()
2919 dig_port->read_infoframe = cpt_read_infoframe; in intel_infoframe_init()
2920 dig_port->set_infoframes = cpt_set_infoframes; in intel_infoframe_init()
2921 dig_port->infoframes_enabled = cpt_infoframes_enabled; in intel_infoframe_init()
2928 struct drm_connector *connector = &intel_connector->base; in intel_hdmi_init_connector()
2929 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; in intel_hdmi_init_connector()
2930 struct intel_encoder *intel_encoder = &dig_port->base; in intel_hdmi_init_connector()
2931 struct drm_device *dev = intel_encoder->base.dev; in intel_hdmi_init_connector()
2934 enum port port = intel_encoder->port; in intel_hdmi_init_connector()
2937 drm_dbg_kms(&dev_priv->drm, in intel_hdmi_init_connector()
2939 intel_encoder->base.base.id, intel_encoder->base.name); in intel_hdmi_init_connector()
2944 if (drm_WARN(dev, dig_port->max_lanes < 4, in intel_hdmi_init_connector()
2946 dig_port->max_lanes, intel_encoder->base.base.id, in intel_hdmi_init_connector()
2947 intel_encoder->base.name)) in intel_hdmi_init_connector()
2950 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder); in intel_hdmi_init_connector()
2951 ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); in intel_hdmi_init_connector()
2959 connector->interlace_allowed = 1; in intel_hdmi_init_connector()
2960 connector->doublescan_allowed = 0; in intel_hdmi_init_connector()
2961 connector->stereo_allowed = 1; in intel_hdmi_init_connector()
2964 connector->ycbcr_420_allowed = true; in intel_hdmi_init_connector()
2966 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; in intel_hdmi_init_connector()
2969 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; in intel_hdmi_init_connector()
2971 intel_connector->get_hw_state = intel_connector_get_hw_state; in intel_hdmi_init_connector()
2976 intel_hdmi->attached_connector = intel_connector; in intel_hdmi_init_connector()
2982 drm_dbg_kms(&dev_priv->drm, in intel_hdmi_init_connector()
2998 intel_hdmi->cec_notifier = in intel_hdmi_init_connector()
2999 cec_notifier_conn_register(dev->dev, port_identifier(port), in intel_hdmi_init_connector()
3001 if (!intel_hdmi->cec_notifier) in intel_hdmi_init_connector()
3002 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n"); in intel_hdmi_init_connector()
3006 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
3030 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
3065 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock; in intel_hdmi_dsc_get_num_slices()
3076 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || in intel_hdmi_dsc_get_num_slices()
3077 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) in intel_hdmi_dsc_get_num_slices()
3100 * clock per slice (in MHz) as read from HF-VSDB. in intel_hdmi_dsc_get_num_slices()
3132 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices); in intel_hdmi_dsc_get_num_slices()
3141 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
3219 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16; in intel_hdmi_dsc_get_bpp()
3230 bpp_target_x16 -= bpp_decrement_x16; in intel_hdmi_dsc_get_bpp()