20  * "The Color Control Surface (CCS) contains the compression status of
22  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
24  *  cache-line-pairs. CCS is always Y tiled."
27  * each cache line in the CCS corresponds to an area of 32x16 cache
29  * us a ratio of one byte in the CCS for each 8x16 pixels in the
44  * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
45  * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
47  * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
146 	} ccs;  member
168 		.ccs.cc_planes = BIT(1),
184 		.ccs.packed_aux_planes = BIT(1),
185 		.ccs.planar_aux_planes = BIT(2) | BIT(3),
193 		.ccs.packed_aux_planes = BIT(1),
201 		.ccs.cc_planes = BIT(2),
202 		.ccs.packed_aux_planes = BIT(1),
210 		.ccs.packed_aux_planes = BIT(1),
218 		.ccs.packed_aux_planes = BIT(1),
304  * intel_fb_is_ccs_modifier: Check if a modifier is a CCS modifier type
318  * intel_fb_is_rc_ccs_cc_modifier: Check if a modifier is an RC CCS CC modifier type
331  * intel_fb_is_mc_ccs_modifier: Check if a modifier is an MC CCS modifier type
423 	if (hweight8(md->ccs.planar_aux_planes) == 2)  in format_is_yuv_semiplanar()
447 		return md->ccs.planar_aux_planes;  in ccs_aux_plane_mask()
449 		return md->ccs.packed_aux_planes;  in ccs_aux_plane_mask()
453  * intel_fb_is_ccs_aux_plane: Check if a framebuffer color plane is a CCS AUX plane
458  * Returns %true if @fb's color plane at index @color_plane is a CCS AUX plane.
468  * intel_fb_is_gen12_ccs_aux_plane: Check if a framebuffer color plane is a GEN12 CCS AUX plane
473  * Returns %true if @fb's color plane at index @color_plane is a GEN12 CCS AUX plane.
484  * intel_fb_rc_ccs_cc_plane: Get the CCS CC color plane index for a framebuffer
495 	if (!md->ccs.cc_planes)  in intel_fb_rc_ccs_cc_plane()
498 	drm_WARN_ON_ONCE(fb->dev, hweight8(md->ccs.cc_planes) > 1);  in intel_fb_rc_ccs_cc_plane()
500 	return ilog2((int)md->ccs.cc_planes);  in intel_fb_rc_ccs_cc_plane()
554 	if (md->ccs.packed_aux_planes | md->ccs.planar_aux_planes)  in skl_main_to_aux_plane()
656  * it's a 64 byte portion of the tile on TGL+ CCS surfaces.
811 	 * TODO: Deduct the subsampling from the char block for all CCS  in intel_fb_plane_get_subsampling()
828 	 * first plane. That's incorrect for the CCS AUX plane of the first  in intel_fb_plane_get_subsampling()
1101 	 * here the main and CCS coordinates must match only within a (64 byte  in intel_fb_check_ccs_xy()
1118 	 * CCS doesn't have its own x/y offset register, so the intra CCS tile  in intel_fb_check_ccs_xy()
1119 	 * x/y offsets must match between CCS and the main surface.  in intel_fb_check_ccs_xy()
1123 			      "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",  in intel_fb_check_ccs_xy()
1156 	 * The new CCS hash mode isn't compatible with remapping as  in intel_plane_can_remap()
1692 	 * The new CCS hash mode makes remapping impossible  in intel_fb_max_stride()
1729 		 * one 64 byte cacheline on the CCS AUX surface.  in intel_fb_stride_alignment()
1978 					    "ccs aux plane %d pitch (%d) must be %d\n",  in intel_framebuffer_init()