Lines Matching refs:free_pos
33 int free_pos; member
139 if (drm_WARN_ON(&dev_priv->drm, dsb->free_pos >= DSB_BUF_SIZE)) { in intel_dsb_indexed_reg_write()
163 dsb->free_pos = ALIGN(dsb->free_pos, 2); in intel_dsb_indexed_reg_write()
165 dsb->ins_start_offset = dsb->free_pos; in intel_dsb_indexed_reg_write()
168 buf[dsb->free_pos++] = 1; in intel_dsb_indexed_reg_write()
171 buf[dsb->free_pos++] = (DSB_OPCODE_INDEXED_WRITE << in intel_dsb_indexed_reg_write()
176 buf[dsb->free_pos++] = val; in intel_dsb_indexed_reg_write()
179 buf[dsb->free_pos++] = val; in intel_dsb_indexed_reg_write()
186 if (dsb->free_pos & 0x1) in intel_dsb_indexed_reg_write()
187 buf[dsb->free_pos] = 0; in intel_dsb_indexed_reg_write()
217 if (drm_WARN_ON(&dev_priv->drm, dsb->free_pos >= DSB_BUF_SIZE)) { in intel_dsb_reg_write()
222 dsb->ins_start_offset = dsb->free_pos; in intel_dsb_reg_write()
223 buf[dsb->free_pos++] = val; in intel_dsb_reg_write()
224 buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) | in intel_dsb_reg_write()
245 if (!(dsb && dsb->free_pos)) in intel_dsb_commit()
259 tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES); in intel_dsb_commit()
260 if (tail > dsb->free_pos * 4) in intel_dsb_commit()
261 memset(&dsb->cmd_buf[dsb->free_pos], 0, in intel_dsb_commit()
262 (tail - dsb->free_pos * 4)); in intel_dsb_commit()
281 dsb->free_pos = 0; in intel_dsb_commit()
337 dsb->free_pos = 0; in intel_dsb_prepare()