Lines Matching +full:hdmi +full:- +full:dp2
103 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
115 return dig_port->base.type == INTEL_OUTPUT_EDP; in intel_dp_is_edp()
124 return crtc_state->port_clock >= 1000000; in intel_dp_is_uhbr()
129 intel_dp->sink_rates[0] = 162000; in intel_dp_set_default_sink_rates()
130 intel_dp->num_sink_rates = 1; in intel_dp_set_default_sink_rates()
142 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) { in intel_dp_set_dpcd_sink_rates()
146 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates)); in intel_dp_set_dpcd_sink_rates()
147 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates); in intel_dp_set_dpcd_sink_rates()
155 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); in intel_dp_set_dpcd_sink_rates()
156 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps); in intel_dp_set_dpcd_sink_rates()
163 intel_dp->sink_rates[i] = dp_rates[i]; in intel_dp_set_dpcd_sink_rates()
170 if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) { in intel_dp_set_dpcd_sink_rates()
173 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3); in intel_dp_set_dpcd_sink_rates()
175 drm_dp_dpcd_readb(&intel_dp->aux, in intel_dp_set_dpcd_sink_rates()
178 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) { in intel_dp_set_dpcd_sink_rates()
180 if (intel_dp->lttpr_common_caps[0] >= 0x20 && in intel_dp_set_dpcd_sink_rates()
181 intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER - in intel_dp_set_dpcd_sink_rates()
185 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES - in intel_dp_set_dpcd_sink_rates()
194 intel_dp->sink_rates[i++] = 1000000; in intel_dp_set_dpcd_sink_rates()
196 intel_dp->sink_rates[i++] = 1350000; in intel_dp_set_dpcd_sink_rates()
198 intel_dp->sink_rates[i++] = 2000000; in intel_dp_set_dpcd_sink_rates()
201 intel_dp->num_sink_rates = i; in intel_dp_set_dpcd_sink_rates()
206 struct intel_connector *connector = intel_dp->attached_connector; in intel_dp_set_sink_rates()
208 struct intel_encoder *encoder = &intel_dig_port->base; in intel_dp_set_sink_rates()
212 if (intel_dp->num_sink_rates) in intel_dp_set_sink_rates()
215 drm_err(&dp_to_i915(intel_dp)->drm, in intel_dp_set_sink_rates()
217 connector->base.base.id, connector->base.name, in intel_dp_set_sink_rates()
218 encoder->base.base.id, encoder->base.name); in intel_dp_set_sink_rates()
225 intel_dp->max_sink_lane_count = 1; in intel_dp_set_default_max_sink_lane_count()
230 struct intel_connector *connector = intel_dp->attached_connector; in intel_dp_set_max_sink_lane_count()
232 struct intel_encoder *encoder = &intel_dig_port->base; in intel_dp_set_max_sink_lane_count()
234 intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); in intel_dp_set_max_sink_lane_count()
236 switch (intel_dp->max_sink_lane_count) { in intel_dp_set_max_sink_lane_count()
243 drm_err(&dp_to_i915(intel_dp)->drm, in intel_dp_set_max_sink_lane_count()
245 connector->base.base.id, connector->base.name, in intel_dp_set_max_sink_lane_count()
246 encoder->base.base.id, encoder->base.name, in intel_dp_set_max_sink_lane_count()
247 intel_dp->max_sink_lane_count); in intel_dp_set_max_sink_lane_count()
259 if (rates[len - i - 1] <= max_rate) in intel_dp_rate_limit_len()
260 return len - i; in intel_dp_rate_limit_len()
270 return intel_dp_rate_limit_len(intel_dp->common_rates, in intel_dp_common_len_rate_limit()
271 intel_dp->num_common_rates, max_rate); in intel_dp_common_len_rate_limit()
276 if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm, in intel_dp_common_rate()
277 index < 0 || index >= intel_dp->num_common_rates)) in intel_dp_common_rate()
280 return intel_dp->common_rates[index]; in intel_dp_common_rate()
286 return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1); in intel_dp_max_common_rate()
291 int vbt_max_lanes = intel_bios_dp_max_lane_count(&dig_port->base); in intel_dp_max_source_lane_count()
292 int max_lanes = dig_port->max_lanes; in intel_dp_max_source_lane_count()
305 int sink_max = intel_dp->max_sink_lane_count; in intel_dp_max_common_lane_count()
307 int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps); in intel_dp_max_common_lane_count()
317 switch (intel_dp->max_link_lane_count) { in intel_dp_max_lane_count()
321 return intel_dp->max_link_lane_count; in intel_dp_max_lane_count()
323 MISSING_CASE(intel_dp->max_link_lane_count); in intel_dp_max_lane_count()
345 * For 8b/10b channel encoding, SST and non-FEC, the data bandwidth efficiency
347 * 162000 kBps. With 8-bit symbols, we have 162000 kHz symbol clock. Just by
354 * kBps. With 32-bit symbols, we have 312500 kHz symbol clock. The value 1000000
376 * 80% data bandwidth efficiency for SST non-FEC. However, this turns in intel_dp_max_data_rate()
390 struct intel_encoder *encoder = &intel_dig_port->base; in intel_dp_can_bigjoiner()
391 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dp_can_bigjoiner()
395 encoder->port != PORT_A); in intel_dp_can_bigjoiner()
406 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); in icl_max_source_rate()
407 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); in icl_max_source_rate()
425 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in vbt_max_link_rate()
431 struct intel_connector *connector = intel_dp->attached_connector; in vbt_max_link_rate()
432 int edp_max_rate = connector->panel.vbt.edp.max_link_rate; in vbt_max_link_rate()
464 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); in intel_dp_set_source_rates()
469 drm_WARN_ON(&dev_priv->drm, in intel_dp_set_source_rates()
470 intel_dp->source_rates || intel_dp->num_source_rates); in intel_dp_set_source_rates()
508 intel_dp->source_rates = source_rates; in intel_dp_set_source_rates()
509 intel_dp->num_source_rates = size; in intel_dp_set_source_rates()
535 /* return index of rate in rates array, or -1 if not found */
544 return -1; in intel_dp_rate_index()
551 drm_WARN_ON(&i915->drm, in intel_dp_set_common_rates()
552 !intel_dp->num_source_rates || !intel_dp->num_sink_rates); in intel_dp_set_common_rates()
554 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates, in intel_dp_set_common_rates()
555 intel_dp->num_source_rates, in intel_dp_set_common_rates()
556 intel_dp->sink_rates, in intel_dp_set_common_rates()
557 intel_dp->num_sink_rates, in intel_dp_set_common_rates()
558 intel_dp->common_rates); in intel_dp_set_common_rates()
561 if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) { in intel_dp_set_common_rates()
562 intel_dp->common_rates[0] = 162000; in intel_dp_set_common_rates()
563 intel_dp->num_common_rates = 1; in intel_dp_set_common_rates()
573 * boot-up. in intel_dp_link_params_valid()
576 link_rate > intel_dp->max_link_rate) in intel_dp_link_params_valid()
592 intel_panel_preferred_fixed_mode(intel_dp->attached_connector); in intel_dp_can_link_train_fallback_for_edp()
595 mode_rate = intel_dp_link_required(fixed_mode->clock, 18); in intel_dp_can_link_train_fallback_for_edp()
613 if (intel_dp->is_mst) { in intel_dp_get_link_train_fallback_values()
614 drm_err(&i915->drm, "Link Training Unsuccessful\n"); in intel_dp_get_link_train_fallback_values()
615 return -1; in intel_dp_get_link_train_fallback_values()
618 if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) { in intel_dp_get_link_train_fallback_values()
619 drm_dbg_kms(&i915->drm, in intel_dp_get_link_train_fallback_values()
621 intel_dp->use_max_params = true; in intel_dp_get_link_train_fallback_values()
625 index = intel_dp_rate_index(intel_dp->common_rates, in intel_dp_get_link_train_fallback_values()
626 intel_dp->num_common_rates, in intel_dp_get_link_train_fallback_values()
631 intel_dp_common_rate(intel_dp, index - 1), in intel_dp_get_link_train_fallback_values()
633 drm_dbg_kms(&i915->drm, in intel_dp_get_link_train_fallback_values()
637 intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1); in intel_dp_get_link_train_fallback_values()
638 intel_dp->max_link_lane_count = lane_count; in intel_dp_get_link_train_fallback_values()
644 drm_dbg_kms(&i915->drm, in intel_dp_get_link_train_fallback_values()
648 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); in intel_dp_get_link_train_fallback_values()
649 intel_dp->max_link_lane_count = lane_count >> 1; in intel_dp_get_link_train_fallback_values()
651 drm_err(&i915->drm, "Link Training Unsuccessful\n"); in intel_dp_get_link_train_fallback_values()
652 return -1; in intel_dp_get_link_train_fallback_values()
687 * for SST -> TimeSlotsPerMTP is 1, in intel_dp_dsc_get_output_bpp()
688 * for MST -> TimeSlotsPerMTP has to be calculated in intel_dp_dsc_get_output_bpp()
708 i915->display.cdclk.max_cdclk_freq * 48 / in intel_dp_dsc_get_output_bpp()
716 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n", in intel_dp_dsc_get_output_bpp()
721 /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */ in intel_dp_dsc_get_output_bpp()
723 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1); in intel_dp_dsc_get_output_bpp()
726 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) { in intel_dp_dsc_get_output_bpp()
755 max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd); in intel_dp_dsc_get_slice_count()
757 drm_dbg_kms(&i915->drm, in intel_dp_dsc_get_slice_count()
772 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false)) in intel_dp_dsc_get_slice_count()
783 drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n", in intel_dp_dsc_get_slice_count()
794 if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output) in intel_dp_output_format()
797 if (intel_dp->dfp.rgb_to_ycbcr && in intel_dp_output_format()
798 intel_dp->dfp.ycbcr_444_to_420) in intel_dp_output_format()
801 if (intel_dp->dfp.ycbcr_444_to_420) in intel_dp_output_format()
832 const struct drm_display_info *info = &connector->base.display_info; in intel_dp_mode_min_output_bpp()
860 struct intel_connector *connector = intel_dp->attached_connector; in intel_dp_max_tmds_clock()
861 const struct drm_display_info *info = &connector->base.display_info; in intel_dp_max_tmds_clock()
862 int max_tmds_clock = intel_dp->dfp.max_tmds_clock; in intel_dp_max_tmds_clock()
864 /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */ in intel_dp_max_tmds_clock()
865 if (max_tmds_clock && info->max_tmds_clock) in intel_dp_max_tmds_clock()
866 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock); in intel_dp_max_tmds_clock()
883 min_tmds_clock = intel_dp->dfp.min_tmds_clock; in intel_dp_tmds_clock_valid()
901 const struct drm_display_info *info = &connector->base.display_info; in intel_dp_mode_valid_downstream()
906 if (intel_dp->dfp.pcon_max_frl_bw) { in intel_dp_mode_valid_downstream()
913 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw; in intel_dp_mode_valid_downstream()
924 if (intel_dp->dfp.max_dotclock && in intel_dp_mode_valid_downstream()
925 target_clock > intel_dp->dfp.max_dotclock) in intel_dp_mode_valid_downstream()
930 /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ in intel_dp_mode_valid_downstream()
936 !connector->base.ycbcr_420_allowed || in intel_dp_mode_valid_downstream()
957 return clock > i915->max_dotclk_freq || hdisplay > 5120; in intel_dp_need_bigjoiner()
966 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); in intel_dp_mode_valid()
968 int target_clock = mode->clock; in intel_dp_mode_valid()
970 int max_dotclk = dev_priv->max_dotclk_freq; in intel_dp_mode_valid()
976 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) in intel_dp_mode_valid()
979 if (mode->flags & DRM_MODE_FLAG_DBLCLK) in intel_dp_mode_valid()
988 target_clock = fixed_mode->clock; in intel_dp_mode_valid()
991 if (mode->clock < 10000) in intel_dp_mode_valid()
994 if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) { in intel_dp_mode_valid()
1008 if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay)) in intel_dp_mode_valid()
1016 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { in intel_dp_mode_valid()
1025 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4; in intel_dp_mode_valid()
1027 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, in intel_dp_mode_valid()
1029 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { in intel_dp_mode_valid()
1035 mode->hdisplay, in intel_dp_mode_valid()
1041 mode->hdisplay, in intel_dp_mode_valid()
1087 len -= r; in snprintf_int_array()
1100 intel_dp->source_rates, intel_dp->num_source_rates); in intel_dp_print_rates()
1101 drm_dbg_kms(&i915->drm, "source rates: %s\n", str); in intel_dp_print_rates()
1104 intel_dp->sink_rates, intel_dp->num_sink_rates); in intel_dp_print_rates()
1105 drm_dbg_kms(&i915->drm, "sink rates: %s\n", str); in intel_dp_print_rates()
1108 intel_dp->common_rates, intel_dp->num_common_rates); in intel_dp_print_rates()
1109 drm_dbg_kms(&i915->drm, "common rates: %s\n", str); in intel_dp_print_rates()
1117 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate); in intel_dp_max_link_rate()
1119 return intel_dp_common_rate(intel_dp, len - 1); in intel_dp_max_link_rate()
1125 int i = intel_dp_rate_index(intel_dp->sink_rates, in intel_dp_rate_select()
1126 intel_dp->num_sink_rates, rate); in intel_dp_rate_select()
1128 if (drm_WARN_ON(&i915->drm, i < 0)) in intel_dp_rate_select()
1138 if (intel_dp->use_rate_select) { in intel_dp_compute_rate()
1157 if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A) in intel_dp_source_supports_fec()
1167 drm_dp_sink_supports_fec(intel_dp->fec_capable); in intel_dp_supports_fec()
1173 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable) in intel_dp_supports_dsc()
1177 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd); in intel_dp_supports_dsc()
1183 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || in intel_dp_is_ycbcr420()
1184 (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 && in intel_dp_is_ycbcr420()
1185 intel_dp->dfp.ycbcr_444_to_420); in intel_dp_is_ycbcr420()
1193 int clock = crtc_state->hw.adjusted_mode.crtc_clock; in intel_dp_hdmi_compute_bpc()
1198 * HDMI minimum is 8bpc however. in intel_dp_hdmi_compute_bpc()
1210 for (; bpc >= 8; bpc -= 2) { in intel_dp_hdmi_compute_bpc()
1212 intel_dp->has_hdmi_sink, ycbcr420_output) && in intel_dp_hdmi_compute_bpc()
1218 return -EINVAL; in intel_dp_hdmi_compute_bpc()
1226 struct intel_connector *intel_connector = intel_dp->attached_connector; in intel_dp_max_bpp()
1229 bpc = crtc_state->pipe_bpp / 3; in intel_dp_max_bpp()
1231 if (intel_dp->dfp.max_bpc) in intel_dp_max_bpp()
1232 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc); in intel_dp_max_bpp()
1234 if (intel_dp->dfp.min_tmds_clock) { in intel_dp_max_bpp()
1248 if (intel_connector->base.display_info.bpc == 0 && in intel_dp_max_bpp()
1249 intel_connector->panel.vbt.edp.bpp && in intel_dp_max_bpp()
1250 intel_connector->panel.vbt.edp.bpp < bpp) { in intel_dp_max_bpp()
1251 drm_dbg_kms(&dev_priv->drm, in intel_dp_max_bpp()
1252 "clamping bpp for eDP panel to BIOS-provided %i\n", in intel_dp_max_bpp()
1253 intel_connector->panel.vbt.edp.bpp); in intel_dp_max_bpp()
1254 bpp = intel_connector->panel.vbt.edp.bpp; in intel_dp_max_bpp()
1270 if (intel_dp->compliance.test_data.bpc != 0) { in intel_dp_adjust_compliance_config()
1271 int bpp = 3 * intel_dp->compliance.test_data.bpc; in intel_dp_adjust_compliance_config()
1273 limits->min_bpp = limits->max_bpp = bpp; in intel_dp_adjust_compliance_config()
1274 pipe_config->dither_force_disable = bpp == 6 * 3; in intel_dp_adjust_compliance_config()
1276 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp); in intel_dp_adjust_compliance_config()
1280 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { in intel_dp_adjust_compliance_config()
1286 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate, in intel_dp_adjust_compliance_config()
1287 intel_dp->compliance.test_lane_count)) { in intel_dp_adjust_compliance_config()
1288 index = intel_dp_rate_index(intel_dp->common_rates, in intel_dp_adjust_compliance_config()
1289 intel_dp->num_common_rates, in intel_dp_adjust_compliance_config()
1290 intel_dp->compliance.test_link_rate); in intel_dp_adjust_compliance_config()
1292 limits->min_rate = limits->max_rate = in intel_dp_adjust_compliance_config()
1293 intel_dp->compliance.test_link_rate; in intel_dp_adjust_compliance_config()
1294 limits->min_lane_count = limits->max_lane_count = in intel_dp_adjust_compliance_config()
1295 intel_dp->compliance.test_lane_count; in intel_dp_adjust_compliance_config()
1302 struct drm_i915_private *i915 = to_i915(connector->base.dev); in has_seamless_m_n()
1315 struct intel_connector *connector = to_intel_connector(conn_state->connector); in intel_dp_mode_clock()
1316 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_dp_mode_clock()
1320 return intel_panel_highest_mode(connector, adjusted_mode)->clock; in intel_dp_mode_clock()
1322 return adjusted_mode->crtc_clock; in intel_dp_mode_clock()
1335 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) { in intel_dp_compute_link_config_wide()
1336 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); in intel_dp_compute_link_config_wide()
1340 for (i = 0; i < intel_dp->num_common_rates; i++) { in intel_dp_compute_link_config_wide()
1342 if (link_rate < limits->min_rate || in intel_dp_compute_link_config_wide()
1343 link_rate > limits->max_rate) in intel_dp_compute_link_config_wide()
1346 for (lane_count = limits->min_lane_count; in intel_dp_compute_link_config_wide()
1347 lane_count <= limits->max_lane_count; in intel_dp_compute_link_config_wide()
1353 pipe_config->lane_count = lane_count; in intel_dp_compute_link_config_wide()
1354 pipe_config->pipe_bpp = bpp; in intel_dp_compute_link_config_wide()
1355 pipe_config->port_clock = link_rate; in intel_dp_compute_link_config_wide()
1363 return -EINVAL; in intel_dp_compute_link_config_wide()
1379 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, in intel_dp_dsc_compute_bpp()
1398 return (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >> in intel_dp_sink_dsc_version_minor()
1405 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_dp_dsc_compute_params()
1407 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dp_dsc_compute_params()
1417 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; in intel_dp_dsc_compute_params()
1418 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; in intel_dp_dsc_compute_params()
1425 if (vdsc_cfg->pic_height % 8 == 0) in intel_dp_dsc_compute_params()
1426 vdsc_cfg->slice_height = 8; in intel_dp_dsc_compute_params()
1427 else if (vdsc_cfg->pic_height % 4 == 0) in intel_dp_dsc_compute_params()
1428 vdsc_cfg->slice_height = 4; in intel_dp_dsc_compute_params()
1430 vdsc_cfg->slice_height = 2; in intel_dp_dsc_compute_params()
1436 vdsc_cfg->dsc_version_major = in intel_dp_dsc_compute_params()
1437 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & in intel_dp_dsc_compute_params()
1439 vdsc_cfg->dsc_version_minor = in intel_dp_dsc_compute_params()
1443 vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & in intel_dp_dsc_compute_params()
1446 line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd); in intel_dp_dsc_compute_params()
1448 drm_dbg_kms(&i915->drm, in intel_dp_dsc_compute_params()
1450 return -EINVAL; in intel_dp_dsc_compute_params()
1453 if (vdsc_cfg->dsc_version_minor == 2) in intel_dp_dsc_compute_params()
1454 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ? in intel_dp_dsc_compute_params()
1457 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ? in intel_dp_dsc_compute_params()
1460 vdsc_cfg->block_pred_enable = in intel_dp_dsc_compute_params()
1461 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & in intel_dp_dsc_compute_params()
1473 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); in intel_dp_dsc_compute_config()
1475 &pipe_config->hw.adjusted_mode; in intel_dp_dsc_compute_config()
1479 pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) && in intel_dp_dsc_compute_config()
1483 return -EINVAL; in intel_dp_dsc_compute_config()
1485 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); in intel_dp_dsc_compute_config()
1487 if (intel_dp->force_dsc_bpc) { in intel_dp_dsc_compute_config()
1488 pipe_bpp = intel_dp->force_dsc_bpc * 3; in intel_dp_dsc_compute_config()
1489 drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp); in intel_dp_dsc_compute_config()
1494 drm_dbg_kms(&dev_priv->drm, in intel_dp_dsc_compute_config()
1496 return -EINVAL; in intel_dp_dsc_compute_config()
1504 pipe_config->pipe_bpp = pipe_bpp; in intel_dp_dsc_compute_config()
1505 pipe_config->port_clock = limits->max_rate; in intel_dp_dsc_compute_config()
1506 pipe_config->lane_count = limits->max_lane_count; in intel_dp_dsc_compute_config()
1509 pipe_config->dsc.compressed_bpp = in intel_dp_dsc_compute_config()
1510 min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4, in intel_dp_dsc_compute_config()
1511 pipe_config->pipe_bpp); in intel_dp_dsc_compute_config()
1512 pipe_config->dsc.slice_count = in intel_dp_dsc_compute_config()
1513 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, in intel_dp_dsc_compute_config()
1521 pipe_config->port_clock, in intel_dp_dsc_compute_config()
1522 pipe_config->lane_count, in intel_dp_dsc_compute_config()
1523 adjusted_mode->crtc_clock, in intel_dp_dsc_compute_config()
1524 adjusted_mode->crtc_hdisplay, in intel_dp_dsc_compute_config()
1525 pipe_config->bigjoiner_pipes, in intel_dp_dsc_compute_config()
1529 adjusted_mode->crtc_clock, in intel_dp_dsc_compute_config()
1530 adjusted_mode->crtc_hdisplay, in intel_dp_dsc_compute_config()
1531 pipe_config->bigjoiner_pipes); in intel_dp_dsc_compute_config()
1533 drm_dbg_kms(&dev_priv->drm, in intel_dp_dsc_compute_config()
1535 return -EINVAL; in intel_dp_dsc_compute_config()
1537 pipe_config->dsc.compressed_bpp = min_t(u16, in intel_dp_dsc_compute_config()
1539 pipe_config->pipe_bpp); in intel_dp_dsc_compute_config()
1540 pipe_config->dsc.slice_count = dsc_dp_slice_count; in intel_dp_dsc_compute_config()
1548 if (adjusted_mode->crtc_clock > dev_priv->display.cdclk.max_cdclk_freq || in intel_dp_dsc_compute_config()
1549 pipe_config->bigjoiner_pipes) { in intel_dp_dsc_compute_config()
1550 if (pipe_config->dsc.slice_count < 2) { in intel_dp_dsc_compute_config()
1551 drm_dbg_kms(&dev_priv->drm, in intel_dp_dsc_compute_config()
1553 return -EINVAL; in intel_dp_dsc_compute_config()
1556 pipe_config->dsc.dsc_split = true; in intel_dp_dsc_compute_config()
1559 ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config); in intel_dp_dsc_compute_config()
1561 drm_dbg_kms(&dev_priv->drm, in intel_dp_dsc_compute_config()
1564 pipe_config->pipe_bpp, in intel_dp_dsc_compute_config()
1565 pipe_config->dsc.compressed_bpp); in intel_dp_dsc_compute_config()
1569 pipe_config->dsc.compression_enable = true; in intel_dp_dsc_compute_config()
1570 drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d " in intel_dp_dsc_compute_config()
1572 pipe_config->pipe_bpp, in intel_dp_dsc_compute_config()
1573 pipe_config->dsc.compressed_bpp, in intel_dp_dsc_compute_config()
1574 pipe_config->dsc.slice_count); in intel_dp_dsc_compute_config()
1585 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_dp_compute_link_config()
1586 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_dp_compute_link_config()
1588 &pipe_config->hw.adjusted_mode; in intel_dp_compute_link_config()
1600 limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format); in intel_dp_compute_link_config()
1603 if (intel_dp->use_max_params) { in intel_dp_compute_link_config()
1618 drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i " in intel_dp_compute_link_config()
1621 limits.max_bpp, adjusted_mode->crtc_clock); in intel_dp_compute_link_config()
1623 if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay, in intel_dp_compute_link_config()
1624 adjusted_mode->crtc_clock)) in intel_dp_compute_link_config()
1625 pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe); in intel_dp_compute_link_config()
1632 joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes; in intel_dp_compute_link_config()
1640 if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) { in intel_dp_compute_link_config()
1641 drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n", in intel_dp_compute_link_config()
1643 str_yes_no(intel_dp->force_dsc_en)); in intel_dp_compute_link_config()
1650 if (pipe_config->dsc.compression_enable) { in intel_dp_compute_link_config()
1651 drm_dbg_kms(&i915->drm, in intel_dp_compute_link_config()
1653 pipe_config->lane_count, pipe_config->port_clock, in intel_dp_compute_link_config()
1654 pipe_config->pipe_bpp, in intel_dp_compute_link_config()
1655 pipe_config->dsc.compressed_bpp); in intel_dp_compute_link_config()
1657 drm_dbg_kms(&i915->drm, in intel_dp_compute_link_config()
1659 intel_dp_link_required(adjusted_mode->crtc_clock, in intel_dp_compute_link_config()
1660 pipe_config->dsc.compressed_bpp), in intel_dp_compute_link_config()
1661 intel_dp_max_data_rate(pipe_config->port_clock, in intel_dp_compute_link_config()
1662 pipe_config->lane_count)); in intel_dp_compute_link_config()
1664 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n", in intel_dp_compute_link_config()
1665 pipe_config->lane_count, pipe_config->port_clock, in intel_dp_compute_link_config()
1666 pipe_config->pipe_bpp); in intel_dp_compute_link_config()
1668 drm_dbg_kms(&i915->drm, in intel_dp_compute_link_config()
1670 intel_dp_link_required(adjusted_mode->crtc_clock, in intel_dp_compute_link_config()
1671 pipe_config->pipe_bpp), in intel_dp_compute_link_config()
1672 intel_dp_max_data_rate(pipe_config->port_clock, in intel_dp_compute_link_config()
1673 pipe_config->lane_count)); in intel_dp_compute_link_config()
1684 &crtc_state->hw.adjusted_mode; in intel_dp_limited_color_range()
1688 * crtc_state->limited_color_range only applies to RGB, in intel_dp_limited_color_range()
1693 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) in intel_dp_limited_color_range()
1696 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { in intel_dp_limited_color_range()
1699 * CEA-861-E - 5.1 Default Encoding Parameters in intel_dp_limited_color_range()
1700 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry in intel_dp_limited_color_range()
1702 return crtc_state->pipe_bpp != 18 && in intel_dp_limited_color_range()
1706 return intel_conn_state->broadcast_rgb == in intel_dp_limited_color_range()
1726 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dp_compute_vsc_colorimetry()
1727 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_dp_compute_vsc_colorimetry()
1730 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 in intel_dp_compute_vsc_colorimetry()
1734 vsc->revision = 0x5; in intel_dp_compute_vsc_colorimetry()
1735 vsc->length = 0x13; in intel_dp_compute_vsc_colorimetry()
1737 /* DP 1.4a spec, Table 2-120 */ in intel_dp_compute_vsc_colorimetry()
1738 switch (crtc_state->output_format) { in intel_dp_compute_vsc_colorimetry()
1740 vsc->pixelformat = DP_PIXELFORMAT_YUV444; in intel_dp_compute_vsc_colorimetry()
1743 vsc->pixelformat = DP_PIXELFORMAT_YUV420; in intel_dp_compute_vsc_colorimetry()
1747 vsc->pixelformat = DP_PIXELFORMAT_RGB; in intel_dp_compute_vsc_colorimetry()
1750 switch (conn_state->colorspace) { in intel_dp_compute_vsc_colorimetry()
1752 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; in intel_dp_compute_vsc_colorimetry()
1755 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601; in intel_dp_compute_vsc_colorimetry()
1758 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709; in intel_dp_compute_vsc_colorimetry()
1761 vsc->colorimetry = DP_COLORIMETRY_SYCC_601; in intel_dp_compute_vsc_colorimetry()
1764 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601; in intel_dp_compute_vsc_colorimetry()
1767 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC; in intel_dp_compute_vsc_colorimetry()
1770 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB; in intel_dp_compute_vsc_colorimetry()
1773 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC; in intel_dp_compute_vsc_colorimetry()
1777 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB; in intel_dp_compute_vsc_colorimetry()
1781 * RGB->YCBCR color conversion uses the BT.709 in intel_dp_compute_vsc_colorimetry()
1784 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) in intel_dp_compute_vsc_colorimetry()
1785 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; in intel_dp_compute_vsc_colorimetry()
1787 vsc->colorimetry = DP_COLORIMETRY_DEFAULT; in intel_dp_compute_vsc_colorimetry()
1791 vsc->bpc = crtc_state->pipe_bpp / 3; in intel_dp_compute_vsc_colorimetry()
1794 drm_WARN_ON(&dev_priv->drm, in intel_dp_compute_vsc_colorimetry()
1795 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB); in intel_dp_compute_vsc_colorimetry()
1798 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA; in intel_dp_compute_vsc_colorimetry()
1799 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; in intel_dp_compute_vsc_colorimetry()
1806 struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc; in intel_dp_compute_vsc_sdp()
1809 if (crtc_state->has_psr) in intel_dp_compute_vsc_sdp()
1815 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); in intel_dp_compute_vsc_sdp()
1816 vsc->sdp_type = DP_SDP_VSC; in intel_dp_compute_vsc_sdp()
1818 &crtc_state->infoframes.vsc); in intel_dp_compute_vsc_sdp()
1826 vsc->sdp_type = DP_SDP_VSC; in intel_dp_compute_psr_vsc_sdp()
1828 if (crtc_state->has_psr2) { in intel_dp_compute_psr_vsc_sdp()
1829 if (intel_dp->psr.colorimetry_support && in intel_dp_compute_psr_vsc_sdp()
1836 * [PSR2, -Colorimetry] in intel_dp_compute_psr_vsc_sdp()
1837 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11 in intel_dp_compute_psr_vsc_sdp()
1838 * 3D stereo + PSR/PSR2 + Y-coordinate. in intel_dp_compute_psr_vsc_sdp()
1840 vsc->revision = 0x4; in intel_dp_compute_psr_vsc_sdp()
1841 vsc->length = 0xe; in intel_dp_compute_psr_vsc_sdp()
1846 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 in intel_dp_compute_psr_vsc_sdp()
1850 vsc->revision = 0x2; in intel_dp_compute_psr_vsc_sdp()
1851 vsc->length = 0x8; in intel_dp_compute_psr_vsc_sdp()
1862 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm; in intel_dp_compute_hdr_metadata_infoframe_sdp()
1864 if (!conn_state->hdr_output_metadata) in intel_dp_compute_hdr_metadata_infoframe_sdp()
1870 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n"); in intel_dp_compute_hdr_metadata_infoframe_sdp()
1874 crtc_state->infoframes.enable |= in intel_dp_compute_hdr_metadata_infoframe_sdp()
1891 struct drm_i915_private *i915 = to_i915(connector->base.dev); in can_enable_drrs()
1893 if (pipe_config->vrr.enable) in can_enable_drrs()
1898 * as it allows more power-savings by complete shutting down display, in can_enable_drrs()
1902 if (pipe_config->has_psr) in can_enable_drrs()
1906 if (pipe_config->has_pch_encoder) in can_enable_drrs()
1909 if (!cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder)) in can_enable_drrs()
1921 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_dp_drrs_compute_config()
1923 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode); in intel_dp_drrs_compute_config()
1927 pipe_config->seamless_m_n = true; in intel_dp_drrs_compute_config()
1930 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder)) in intel_dp_drrs_compute_config()
1931 intel_zero_m_n(&pipe_config->dp_m2_n2); in intel_dp_drrs_compute_config()
1936 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay; in intel_dp_drrs_compute_config()
1938 pipe_config->has_drrs = true; in intel_dp_drrs_compute_config()
1940 pixel_clock = downclock_mode->clock; in intel_dp_drrs_compute_config()
1941 if (pipe_config->splitter.enable) in intel_dp_drrs_compute_config()
1942 pixel_clock /= pipe_config->splitter.link_count; in intel_dp_drrs_compute_config()
1944 intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock, in intel_dp_drrs_compute_config()
1945 pipe_config->port_clock, &pipe_config->dp_m2_n2, in intel_dp_drrs_compute_config()
1946 pipe_config->fec_enable); in intel_dp_drrs_compute_config()
1949 if (pipe_config->splitter.enable) in intel_dp_drrs_compute_config()
1950 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count; in intel_dp_drrs_compute_config()
1957 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_dp_has_audio()
1962 if (!intel_dp_port_has_audio(i915, encoder->port)) in intel_dp_has_audio()
1965 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) in intel_dp_has_audio()
1966 return intel_dp->has_audio; in intel_dp_has_audio()
1968 return intel_conn_state->force_audio == HDMI_AUDIO_ON; in intel_dp_has_audio()
1977 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_dp_compute_output_format()
1979 struct intel_connector *connector = intel_dp->attached_connector; in intel_dp_compute_output_format()
1980 const struct drm_display_info *info = &connector->base.display_info; in intel_dp_compute_output_format()
1981 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_dp_compute_output_format()
1987 crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only); in intel_dp_compute_output_format()
1990 drm_dbg_kms(&i915->drm, in intel_dp_compute_output_format()
1992 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_dp_compute_output_format()
1999 !connector->base.ycbcr_420_allowed || in intel_dp_compute_output_format()
2003 crtc_state->output_format = intel_dp_output_format(connector, true); in intel_dp_compute_output_format()
2016 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dp_compute_config()
2017 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dp_compute_config()
2020 struct intel_connector *connector = intel_dp->attached_connector; in intel_dp_compute_config()
2023 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A) in intel_dp_compute_config()
2024 pipe_config->has_pch_encoder = true; in intel_dp_compute_config()
2026 pipe_config->has_audio = intel_dp_has_audio(encoder, pipe_config, conn_state); in intel_dp_compute_config()
2035 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in intel_dp_compute_config()
2036 return -EINVAL; in intel_dp_compute_config()
2039 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) in intel_dp_compute_config()
2040 return -EINVAL; in intel_dp_compute_config()
2042 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) in intel_dp_compute_config()
2043 return -EINVAL; in intel_dp_compute_config()
2045 if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay)) in intel_dp_compute_config()
2046 return -EINVAL; in intel_dp_compute_config()
2059 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { in intel_dp_compute_config()
2065 pipe_config->limited_color_range = in intel_dp_compute_config()
2068 if (pipe_config->dsc.compression_enable) in intel_dp_compute_config()
2069 output_bpp = pipe_config->dsc.compressed_bpp; in intel_dp_compute_config()
2071 output_bpp = intel_dp_output_bpp(pipe_config->output_format, in intel_dp_compute_config()
2072 pipe_config->pipe_bpp); in intel_dp_compute_config()
2074 if (intel_dp->mso_link_count) { in intel_dp_compute_config()
2075 int n = intel_dp->mso_link_count; in intel_dp_compute_config()
2076 int overlap = intel_dp->mso_pixel_overlap; in intel_dp_compute_config()
2078 pipe_config->splitter.enable = true; in intel_dp_compute_config()
2079 pipe_config->splitter.link_count = n; in intel_dp_compute_config()
2080 pipe_config->splitter.pixel_overlap = overlap; in intel_dp_compute_config()
2082 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n", in intel_dp_compute_config()
2085 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap; in intel_dp_compute_config()
2086 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap; in intel_dp_compute_config()
2087 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap; in intel_dp_compute_config()
2088 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap; in intel_dp_compute_config()
2089 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap; in intel_dp_compute_config()
2090 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap; in intel_dp_compute_config()
2091 adjusted_mode->crtc_clock /= n; in intel_dp_compute_config()
2095 pipe_config->lane_count, in intel_dp_compute_config()
2096 adjusted_mode->crtc_clock, in intel_dp_compute_config()
2097 pipe_config->port_clock, in intel_dp_compute_config()
2098 &pipe_config->dp_m_n, in intel_dp_compute_config()
2099 pipe_config->fec_enable); in intel_dp_compute_config()
2102 if (pipe_config->splitter.enable) in intel_dp_compute_config()
2103 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count; in intel_dp_compute_config()
2120 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); in intel_dp_set_link_params()
2121 intel_dp->link_trained = false; in intel_dp_set_link_params()
2122 intel_dp->link_rate = link_rate; in intel_dp_set_link_params()
2123 intel_dp->lane_count = lane_count; in intel_dp_set_link_params()
2128 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); in intel_dp_reset_max_link_params()
2129 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); in intel_dp_reset_max_link_params()
2136 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder)); in intel_edp_backlight_on()
2142 drm_dbg_kms(&i915->drm, "\n"); in intel_edp_backlight_on()
2151 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)); in intel_edp_backlight_off()
2157 drm_dbg_kms(&i915->drm, "\n"); in intel_edp_backlight_off()
2173 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && in downstream_hpd_needs_d0()
2174 drm_dp_is_branch(intel_dp->dpcd) && in downstream_hpd_needs_d0()
2175 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; in downstream_hpd_needs_d0()
2185 if (!crtc_state->dsc.compression_enable) in intel_dp_sink_set_decompression_state()
2188 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE, in intel_dp_sink_set_decompression_state()
2191 drm_dbg_kms(&i915->drm, in intel_dp_sink_set_decompression_state()
2208 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0) in intel_edp_init_source_oui()
2209 drm_err(&i915->drm, "Failed to read source OUI\n"); in intel_edp_init_source_oui()
2215 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) in intel_edp_init_source_oui()
2216 drm_err(&i915->drm, "Failed to write source OUI\n"); in intel_edp_init_source_oui()
2218 intel_dp->last_oui_write = jiffies; in intel_edp_init_source_oui()
2225 drm_dbg_kms(&i915->drm, "Performing OUI wait\n"); in intel_dp_wait_source_oui()
2226 wait_remaining_ms_from_jiffies(intel_dp->last_oui_write, 30); in intel_dp_wait_source_oui()
2232 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_dp_set_power()
2233 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_dp_set_power()
2237 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in intel_dp_set_power()
2244 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); in intel_dp_set_power()
2259 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); in intel_dp_set_power()
2265 if (ret == 1 && lspcon->active) in intel_dp_set_power()
2270 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n", in intel_dp_set_power()
2271 encoder->base.base.id, encoder->base.name, in intel_dp_set_power()
2279 * intel_dp_sync_state - sync the encoder state during init/resume
2298 if (intel_dp->dpcd[DP_DPCD_REV] == 0) in intel_dp_sync_state()
2307 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_dp_initial_fastset_check()
2311 * If BIOS has set an unsupported or non-standard link rate for some in intel_dp_initial_fastset_check()
2314 if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates, in intel_dp_initial_fastset_check()
2315 crtc_state->port_clock) < 0) { in intel_dp_initial_fastset_check()
2316 drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n"); in intel_dp_initial_fastset_check()
2317 crtc_state->uapi.connectors_changed = true; in intel_dp_initial_fastset_check()
2325 * of crtc_state->dsc, we have no way to ensure reliable fastset. in intel_dp_initial_fastset_check()
2328 if (crtc_state->dsc.compression_enable) { in intel_dp_initial_fastset_check()
2329 drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n"); in intel_dp_initial_fastset_check()
2330 crtc_state->uapi.mode_changed = true; in intel_dp_initial_fastset_check()
2335 drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n"); in intel_dp_initial_fastset_check()
2336 crtc_state->uapi.mode_changed = true; in intel_dp_initial_fastset_check()
2349 memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); in intel_dp_get_pcon_dsc_cap()
2351 if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, in intel_dp_get_pcon_dsc_cap()
2352 intel_dp->pcon_dsc_dpcd, in intel_dp_get_pcon_dsc_cap()
2353 sizeof(intel_dp->pcon_dsc_dpcd)) < 0) in intel_dp_get_pcon_dsc_cap()
2354 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n", in intel_dp_get_pcon_dsc_cap()
2357 drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n", in intel_dp_get_pcon_dsc_cap()
2358 (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd); in intel_dp_get_pcon_dsc_cap()
2366 for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) { in intel_dp_pcon_get_frl_mask()
2395 struct intel_connector *intel_connector = intel_dp->attached_connector; in intel_dp_hdmi_sink_max_frl()
2396 struct drm_connector *connector = &intel_connector->base; in intel_dp_hdmi_sink_max_frl()
2401 max_lanes = connector->display_info.hdmi.max_lanes; in intel_dp_hdmi_sink_max_frl()
2402 rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane; in intel_dp_hdmi_sink_max_frl()
2405 if (connector->display_info.hdmi.dsc_cap.v_1p2) { in intel_dp_hdmi_sink_max_frl()
2406 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes; in intel_dp_hdmi_sink_max_frl()
2407 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane; in intel_dp_hdmi_sink_max_frl()
2419 if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) && in intel_dp_pcon_is_frl_trained()
2420 drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL && in intel_dp_pcon_is_frl_trained()
2437 max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw; in intel_dp_pcon_start_frl_training()
2438 drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw); in intel_dp_pcon_start_frl_training()
2441 drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw); in intel_dp_pcon_start_frl_training()
2446 return -EINVAL; in intel_dp_pcon_start_frl_training()
2449 drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask); in intel_dp_pcon_start_frl_training()
2454 ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false); in intel_dp_pcon_start_frl_training()
2458 wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS); in intel_dp_pcon_start_frl_training()
2461 return -ETIMEDOUT; in intel_dp_pcon_start_frl_training()
2463 ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, in intel_dp_pcon_start_frl_training()
2467 ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, in intel_dp_pcon_start_frl_training()
2471 ret = drm_dp_pcon_frl_enable(&intel_dp->aux); in intel_dp_pcon_start_frl_training()
2476 * Check if the HDMI Link is up and active. in intel_dp_pcon_start_frl_training()
2483 return -ETIMEDOUT; in intel_dp_pcon_start_frl_training()
2486 drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask); in intel_dp_pcon_start_frl_training()
2487 intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask); in intel_dp_pcon_start_frl_training()
2488 intel_dp->frl.is_trained = true; in intel_dp_pcon_start_frl_training()
2489 drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps); in intel_dp_pcon_start_frl_training()
2496 if (drm_dp_is_branch(intel_dp->dpcd) && in intel_dp_is_hdmi_2_1_sink()
2497 intel_dp->has_hdmi_sink && in intel_dp_is_hdmi_2_1_sink()
2513 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); in intel_dp_pcon_set_tmds_mode()
2517 /* Set HDMI LINK ENABLE */ in intel_dp_pcon_set_tmds_mode()
2519 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); in intel_dp_pcon_set_tmds_mode()
2532 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7) in intel_dp_check_frl_training()
2533 * -sink is HDMI2.1 in intel_dp_check_frl_training()
2535 if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) || in intel_dp_check_frl_training()
2537 intel_dp->frl.is_trained) in intel_dp_check_frl_training()
2543 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n"); in intel_dp_check_frl_training()
2545 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL); in intel_dp_check_frl_training()
2548 drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n"); in intel_dp_check_frl_training()
2550 drm_dbg(&dev_priv->drm, "FRL training Completed\n"); in intel_dp_check_frl_training()
2557 int vactive = crtc_state->hw.adjusted_mode.vdisplay; in intel_dp_pcon_dsc_enc_slice_height()
2566 struct intel_connector *intel_connector = intel_dp->attached_connector; in intel_dp_pcon_dsc_enc_slices()
2567 struct drm_connector *connector = &intel_connector->base; in intel_dp_pcon_dsc_enc_slices()
2568 int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice; in intel_dp_pcon_dsc_enc_slices()
2569 int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices; in intel_dp_pcon_dsc_enc_slices()
2570 int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd); in intel_dp_pcon_dsc_enc_slices()
2571 int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd); in intel_dp_pcon_dsc_enc_slices()
2583 struct intel_connector *intel_connector = intel_dp->attached_connector; in intel_dp_pcon_dsc_enc_bpp()
2584 struct drm_connector *connector = &intel_connector->base; in intel_dp_pcon_dsc_enc_bpp()
2585 int output_format = crtc_state->output_format; in intel_dp_pcon_dsc_enc_bpp()
2586 bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp; in intel_dp_pcon_dsc_enc_bpp()
2587 int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd); in intel_dp_pcon_dsc_enc_bpp()
2589 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024; in intel_dp_pcon_dsc_enc_bpp()
2606 struct intel_connector *intel_connector = intel_dp->attached_connector; in intel_dp_pcon_dsc_configure()
2616 connector = &intel_connector->base; in intel_dp_pcon_dsc_configure()
2617 hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2; in intel_dp_pcon_dsc_configure()
2619 if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) || in intel_dp_pcon_dsc_configure()
2631 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, in intel_dp_pcon_dsc_configure()
2646 ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param); in intel_dp_pcon_dsc_configure()
2648 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n"); in intel_dp_pcon_dsc_configure()
2657 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13) in intel_dp_configure_protocol_converter()
2660 if (!drm_dp_is_branch(intel_dp->dpcd)) in intel_dp_configure_protocol_converter()
2663 tmp = intel_dp->has_hdmi_sink ? in intel_dp_configure_protocol_converter()
2666 if (drm_dp_dpcd_writeb(&intel_dp->aux, in intel_dp_configure_protocol_converter()
2668 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n", in intel_dp_configure_protocol_converter()
2669 str_enable_disable(intel_dp->has_hdmi_sink)); in intel_dp_configure_protocol_converter()
2671 tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 && in intel_dp_configure_protocol_converter()
2672 intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0; in intel_dp_configure_protocol_converter()
2674 if (drm_dp_dpcd_writeb(&intel_dp->aux, in intel_dp_configure_protocol_converter()
2676 drm_dbg_kms(&i915->drm, in intel_dp_configure_protocol_converter()
2678 str_enable_disable(intel_dp->dfp.ycbcr_444_to_420)); in intel_dp_configure_protocol_converter()
2680 tmp = intel_dp->dfp.rgb_to_ycbcr ? in intel_dp_configure_protocol_converter()
2683 if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0) in intel_dp_configure_protocol_converter()
2684 drm_dbg_kms(&i915->drm, in intel_dp_configure_protocol_converter()
2685 "Failed to %s protocol converter RGB->YCbCr conversion mode\n", in intel_dp_configure_protocol_converter()
2694 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, in intel_dp_get_colorimetry_status()
2708 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); in intel_dp_get_dsc_sink_cap()
2711 intel_dp->fec_capable = 0; in intel_dp_get_dsc_sink_cap()
2714 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 || in intel_dp_get_dsc_sink_cap()
2715 intel_dp->edp_dpcd[0] >= DP_EDP_14) { in intel_dp_get_dsc_sink_cap()
2716 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT, in intel_dp_get_dsc_sink_cap()
2717 intel_dp->dsc_dpcd, in intel_dp_get_dsc_sink_cap()
2718 sizeof(intel_dp->dsc_dpcd)) < 0) in intel_dp_get_dsc_sink_cap()
2719 drm_err(&i915->drm, in intel_dp_get_dsc_sink_cap()
2723 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n", in intel_dp_get_dsc_sink_cap()
2724 (int)sizeof(intel_dp->dsc_dpcd), in intel_dp_get_dsc_sink_cap()
2725 intel_dp->dsc_dpcd); in intel_dp_get_dsc_sink_cap()
2729 drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY, in intel_dp_get_dsc_sink_cap()
2730 &intel_dp->fec_capable) < 0) in intel_dp_get_dsc_sink_cap()
2731 drm_err(&i915->drm, in intel_dp_get_dsc_sink_cap()
2734 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n", in intel_dp_get_dsc_sink_cap()
2735 intel_dp->fec_capable); in intel_dp_get_dsc_sink_cap()
2743 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_edp_mso_mode_fixup()
2744 int n = intel_dp->mso_link_count; in intel_edp_mso_mode_fixup()
2745 int overlap = intel_dp->mso_pixel_overlap; in intel_edp_mso_mode_fixup()
2750 mode->hdisplay = (mode->hdisplay - overlap) * n; in intel_edp_mso_mode_fixup()
2751 mode->hsync_start = (mode->hsync_start - overlap) * n; in intel_edp_mso_mode_fixup()
2752 mode->hsync_end = (mode->hsync_end - overlap) * n; in intel_edp_mso_mode_fixup()
2753 mode->htotal = (mode->htotal - overlap) * n; in intel_edp_mso_mode_fixup()
2754 mode->clock *= n; in intel_edp_mso_mode_fixup()
2758 drm_dbg_kms(&i915->drm, in intel_edp_mso_mode_fixup()
2760 connector->base.base.id, connector->base.name, in intel_edp_mso_mode_fixup()
2766 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_edp_fixup_vbt_bpp()
2768 struct intel_connector *connector = intel_dp->attached_connector; in intel_edp_fixup_vbt_bpp()
2770 if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) { in intel_edp_fixup_vbt_bpp()
2784 drm_dbg_kms(&dev_priv->drm, in intel_edp_fixup_vbt_bpp()
2785 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", in intel_edp_fixup_vbt_bpp()
2786 pipe_bpp, connector->panel.vbt.edp.bpp); in intel_edp_fixup_vbt_bpp()
2787 connector->panel.vbt.edp.bpp = pipe_bpp; in intel_edp_fixup_vbt_bpp()
2794 struct intel_connector *connector = intel_dp->attached_connector; in intel_edp_mso_init()
2795 struct drm_display_info *info = &connector->base.display_info; in intel_edp_mso_init()
2798 if (intel_dp->edp_dpcd[0] < DP_EDP_14) in intel_edp_mso_init()
2801 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) { in intel_edp_mso_init()
2802 drm_err(&i915->drm, "Failed to read MSO cap\n"); in intel_edp_mso_init()
2808 if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) { in intel_edp_mso_init()
2809 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso); in intel_edp_mso_init()
2814 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n", in intel_edp_mso_init()
2815 mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso, in intel_edp_mso_init()
2816 info->mso_pixel_overlap); in intel_edp_mso_init()
2818 drm_err(&i915->drm, "No source MSO support, disabling\n"); in intel_edp_mso_init()
2823 intel_dp->mso_link_count = mso; in intel_edp_mso_init()
2824 intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0; in intel_edp_mso_init()
2831 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); in intel_edp_init_dpcd()
2834 drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0); in intel_edp_init_dpcd()
2836 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) in intel_edp_init_dpcd()
2839 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, in intel_edp_init_dpcd()
2840 drm_dp_is_branch(intel_dp->dpcd)); in intel_edp_init_dpcd()
2851 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, in intel_edp_init_dpcd()
2852 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == in intel_edp_init_dpcd()
2853 sizeof(intel_dp->edp_dpcd)) { in intel_edp_init_dpcd()
2854 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n", in intel_edp_init_dpcd()
2855 (int)sizeof(intel_dp->edp_dpcd), in intel_edp_init_dpcd()
2856 intel_dp->edp_dpcd); in intel_edp_init_dpcd()
2858 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14; in intel_edp_init_dpcd()
2862 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks in intel_edp_init_dpcd()
2863 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1] in intel_edp_init_dpcd()
2868 intel_dp->num_sink_rates = 0; in intel_edp_init_dpcd()
2871 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) { in intel_edp_init_dpcd()
2875 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, in intel_edp_init_dpcd()
2884 /* Value read multiplied by 200kHz gives the per-lane in intel_edp_init_dpcd()
2890 intel_dp->sink_rates[i] = (val * 200) / 10; in intel_edp_init_dpcd()
2892 intel_dp->num_sink_rates = i; in intel_edp_init_dpcd()
2899 if (intel_dp->num_sink_rates) in intel_edp_init_dpcd()
2900 intel_dp->use_rate_select = true; in intel_edp_init_dpcd()
2910 * If needed, program our source OUI so we can make various Intel-specific AUX services in intel_edp_init_dpcd()
2921 if (!intel_dp->attached_connector) in intel_dp_has_sink_count()
2924 return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base, in intel_dp_has_sink_count()
2925 intel_dp->dpcd, in intel_dp_has_sink_count()
2926 &intel_dp->desc); in intel_dp_has_sink_count()
2938 * Don't clobber cached eDP rates. Also skip re-reading in intel_dp_get_dpcd()
2942 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, in intel_dp_get_dpcd()
2943 drm_dp_is_branch(intel_dp->dpcd)); in intel_dp_get_dpcd()
2951 ret = drm_dp_read_sink_count(&intel_dp->aux); in intel_dp_get_dpcd()
2960 intel_dp->sink_count = ret; in intel_dp_get_dpcd()
2969 if (!intel_dp->sink_count) in intel_dp_get_dpcd()
2973 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd, in intel_dp_get_dpcd()
2974 intel_dp->downstream_ports) == 0; in intel_dp_get_dpcd()
2982 return i915->params.enable_dp_mst && in intel_dp_can_mst()
2984 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd); in intel_dp_can_mst()
2992 &dp_to_dig_port(intel_dp)->base; in intel_dp_configure_mst()
2993 bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd); in intel_dp_configure_mst()
2995 drm_dbg_kms(&i915->drm, in intel_dp_configure_mst()
2997 encoder->base.base.id, encoder->base.name, in intel_dp_configure_mst()
3000 str_yes_no(i915->params.enable_dp_mst)); in intel_dp_configure_mst()
3005 intel_dp->is_mst = sink_can_mst && in intel_dp_configure_mst()
3006 i915->params.enable_dp_mst; in intel_dp_configure_mst()
3008 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, in intel_dp_configure_mst()
3009 intel_dp->is_mst); in intel_dp_configure_mst()
3015 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4; in intel_dp_get_sink_irq_esi()
3023 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1, in intel_dp_ack_sink_irq_esi()
3040 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) in intel_dp_needs_vsc_sdp()
3043 switch (conn_state->colorspace) { in intel_dp_needs_vsc_sdp()
3063 return -ENOSPC; in intel_dp_vsc_sdp_pack()
3068 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 in intel_dp_vsc_sdp_pack()
3071 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */ in intel_dp_vsc_sdp_pack()
3072 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */ in intel_dp_vsc_sdp_pack()
3073 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */ in intel_dp_vsc_sdp_pack()
3074 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */ in intel_dp_vsc_sdp_pack()
3080 if (vsc->revision != 0x5) in intel_dp_vsc_sdp_pack()
3085 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */ in intel_dp_vsc_sdp_pack()
3086 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */ in intel_dp_vsc_sdp_pack()
3088 switch (vsc->bpc) { in intel_dp_vsc_sdp_pack()
3093 sdp->db[17] = 0x1; /* DB17[3:0] */ in intel_dp_vsc_sdp_pack()
3096 sdp->db[17] = 0x2; in intel_dp_vsc_sdp_pack()
3099 sdp->db[17] = 0x3; in intel_dp_vsc_sdp_pack()
3102 sdp->db[17] = 0x4; in intel_dp_vsc_sdp_pack()
3105 MISSING_CASE(vsc->bpc); in intel_dp_vsc_sdp_pack()
3109 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) in intel_dp_vsc_sdp_pack()
3110 sdp->db[17] |= 0x80; /* DB17[7] */ in intel_dp_vsc_sdp_pack()
3113 sdp->db[18] = vsc->content_type & 0x7; in intel_dp_vsc_sdp_pack()
3131 return -ENOSPC; in intel_dp_hdr_metadata_infoframe_sdp_pack()
3137 drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n"); in intel_dp_hdr_metadata_infoframe_sdp_pack()
3138 return -ENOSPC; in intel_dp_hdr_metadata_infoframe_sdp_pack()
3142 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n"); in intel_dp_hdr_metadata_infoframe_sdp_pack()
3143 return -ENOSPC; in intel_dp_hdr_metadata_infoframe_sdp_pack()
3149 * Table 2-100 and Table 2-101 in intel_dp_hdr_metadata_infoframe_sdp_pack()
3152 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */ in intel_dp_hdr_metadata_infoframe_sdp_pack()
3153 sdp->sdp_header.HB0 = 0; in intel_dp_hdr_metadata_infoframe_sdp_pack()
3155 * Packet Type 80h + Non-audio INFOFRAME Type value in intel_dp_hdr_metadata_infoframe_sdp_pack()
3157 * - 80h + Non-audio INFOFRAME Type value in intel_dp_hdr_metadata_infoframe_sdp_pack()
3158 * - InfoFrame Type: 0x07 in intel_dp_hdr_metadata_infoframe_sdp_pack()
3159 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame] in intel_dp_hdr_metadata_infoframe_sdp_pack()
3161 sdp->sdp_header.HB1 = drm_infoframe->type; in intel_dp_hdr_metadata_infoframe_sdp_pack()
3164 * infoframe_size - 1 in intel_dp_hdr_metadata_infoframe_sdp_pack()
3166 sdp->sdp_header.HB2 = 0x1D; in intel_dp_hdr_metadata_infoframe_sdp_pack()
3168 sdp->sdp_header.HB3 = (0x13 << 2); in intel_dp_hdr_metadata_infoframe_sdp_pack()
3170 sdp->db[0] = drm_infoframe->version; in intel_dp_hdr_metadata_infoframe_sdp_pack()
3172 sdp->db[1] = drm_infoframe->length; in intel_dp_hdr_metadata_infoframe_sdp_pack()
3177 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2); in intel_dp_hdr_metadata_infoframe_sdp_pack()
3178 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE], in intel_dp_hdr_metadata_infoframe_sdp_pack()
3183 * - DP SDP Header(struct dp_sdp_header): 4 bytes in intel_dp_hdr_metadata_infoframe_sdp_pack()
3184 * - Two Data Blocks: 2 bytes in intel_dp_hdr_metadata_infoframe_sdp_pack()
3187 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes in intel_dp_hdr_metadata_infoframe_sdp_pack()
3201 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_write_dp_sdp()
3205 if ((crtc_state->infoframes.enable & in intel_write_dp_sdp()
3211 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp, in intel_write_dp_sdp()
3216 &crtc_state->infoframes.drm.drm, in intel_write_dp_sdp()
3224 if (drm_WARN_ON(&dev_priv->drm, len < 0)) in intel_write_dp_sdp()
3227 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len); in intel_write_dp_sdp()
3235 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_write_dp_vsc_sdp()
3241 if (drm_WARN_ON(&dev_priv->drm, len < 0)) in intel_write_dp_vsc_sdp()
3244 dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC, in intel_write_dp_vsc_sdp()
3253 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dp_set_infoframes()
3254 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); in intel_dp_set_infoframes()
3262 if (!crtc_state->has_psr) in intel_dp_set_infoframes()
3272 if (!crtc_state->has_psr) in intel_dp_set_infoframes()
3284 return -EINVAL; in intel_dp_vsc_sdp_unpack()
3288 if (sdp->sdp_header.HB0 != 0) in intel_dp_vsc_sdp_unpack()
3289 return -EINVAL; in intel_dp_vsc_sdp_unpack()
3291 if (sdp->sdp_header.HB1 != DP_SDP_VSC) in intel_dp_vsc_sdp_unpack()
3292 return -EINVAL; in intel_dp_vsc_sdp_unpack()
3294 vsc->sdp_type = sdp->sdp_header.HB1; in intel_dp_vsc_sdp_unpack()
3295 vsc->revision = sdp->sdp_header.HB2; in intel_dp_vsc_sdp_unpack()
3296 vsc->length = sdp->sdp_header.HB3; in intel_dp_vsc_sdp_unpack()
3298 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) || in intel_dp_vsc_sdp_unpack()
3299 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) { in intel_dp_vsc_sdp_unpack()
3301 * - HB2 = 0x2, HB3 = 0x8 in intel_dp_vsc_sdp_unpack()
3303 * - HB2 = 0x4, HB3 = 0xe in intel_dp_vsc_sdp_unpack()
3304 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of in intel_dp_vsc_sdp_unpack()
3309 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) { in intel_dp_vsc_sdp_unpack()
3311 * - HB2 = 0x5, HB3 = 0x13 in intel_dp_vsc_sdp_unpack()
3315 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf; in intel_dp_vsc_sdp_unpack()
3316 vsc->colorimetry = sdp->db[16] & 0xf; in intel_dp_vsc_sdp_unpack()
3317 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1; in intel_dp_vsc_sdp_unpack()
3319 switch (sdp->db[17] & 0x7) { in intel_dp_vsc_sdp_unpack()
3321 vsc->bpc = 6; in intel_dp_vsc_sdp_unpack()
3324 vsc->bpc = 8; in intel_dp_vsc_sdp_unpack()
3327 vsc->bpc = 10; in intel_dp_vsc_sdp_unpack()
3330 vsc->bpc = 12; in intel_dp_vsc_sdp_unpack()
3333 vsc->bpc = 16; in intel_dp_vsc_sdp_unpack()
3336 MISSING_CASE(sdp->db[17] & 0x7); in intel_dp_vsc_sdp_unpack()
3337 return -EINVAL; in intel_dp_vsc_sdp_unpack()
3340 vsc->content_type = sdp->db[18] & 0x7; in intel_dp_vsc_sdp_unpack()
3342 return -EINVAL; in intel_dp_vsc_sdp_unpack()
3357 return -EINVAL; in intel_dp_hdr_metadata_infoframe_sdp_unpack()
3359 if (sdp->sdp_header.HB0 != 0) in intel_dp_hdr_metadata_infoframe_sdp_unpack()
3360 return -EINVAL; in intel_dp_hdr_metadata_infoframe_sdp_unpack()
3362 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM) in intel_dp_hdr_metadata_infoframe_sdp_unpack()
3363 return -EINVAL; in intel_dp_hdr_metadata_infoframe_sdp_unpack()
3369 if (sdp->sdp_header.HB2 != 0x1D) in intel_dp_hdr_metadata_infoframe_sdp_unpack()
3370 return -EINVAL; in intel_dp_hdr_metadata_infoframe_sdp_unpack()
3373 if ((sdp->sdp_header.HB3 & 0x3) != 0) in intel_dp_hdr_metadata_infoframe_sdp_unpack()
3374 return -EINVAL; in intel_dp_hdr_metadata_infoframe_sdp_unpack()
3377 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13) in intel_dp_hdr_metadata_infoframe_sdp_unpack()
3378 return -EINVAL; in intel_dp_hdr_metadata_infoframe_sdp_unpack()
3381 if (sdp->db[0] != 1) in intel_dp_hdr_metadata_infoframe_sdp_unpack()
3382 return -EINVAL; in intel_dp_hdr_metadata_infoframe_sdp_unpack()
3385 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE) in intel_dp_hdr_metadata_infoframe_sdp_unpack()
3386 return -EINVAL; in intel_dp_hdr_metadata_infoframe_sdp_unpack()
3388 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2], in intel_dp_hdr_metadata_infoframe_sdp_unpack()
3399 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_read_dp_vsc_sdp()
3405 if (crtc_state->has_psr) in intel_read_dp_vsc_sdp()
3408 if ((crtc_state->infoframes.enable & in intel_read_dp_vsc_sdp()
3412 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp)); in intel_read_dp_vsc_sdp()
3417 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n"); in intel_read_dp_vsc_sdp()
3425 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_read_dp_hdr_metadata_infoframe_sdp()
3430 if ((crtc_state->infoframes.enable & in intel_read_dp_hdr_metadata_infoframe_sdp()
3434 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, in intel_read_dp_hdr_metadata_infoframe_sdp()
3441 drm_dbg_kms(&dev_priv->drm, in intel_read_dp_hdr_metadata_infoframe_sdp()
3452 &crtc_state->infoframes.vsc); in intel_read_dp_sdp()
3456 &crtc_state->infoframes.drm.drm); in intel_read_dp_sdp()
3474 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT, in intel_dp_autotest_link_training()
3478 drm_dbg_kms(&i915->drm, "Lane count read failed\n"); in intel_dp_autotest_link_training()
3483 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE, in intel_dp_autotest_link_training()
3486 drm_dbg_kms(&i915->drm, "Link Rate read failed\n"); in intel_dp_autotest_link_training()
3496 intel_dp->compliance.test_lane_count = test_lane_count; in intel_dp_autotest_link_training()
3497 intel_dp->compliance.test_link_rate = test_link_rate; in intel_dp_autotest_link_training()
3511 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN, in intel_dp_autotest_video_pattern()
3514 drm_dbg_kms(&i915->drm, "Test pattern read failed\n"); in intel_dp_autotest_video_pattern()
3520 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI, in intel_dp_autotest_video_pattern()
3523 drm_dbg_kms(&i915->drm, "H Width read failed\n"); in intel_dp_autotest_video_pattern()
3527 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI, in intel_dp_autotest_video_pattern()
3530 drm_dbg_kms(&i915->drm, "V Height read failed\n"); in intel_dp_autotest_video_pattern()
3534 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0, in intel_dp_autotest_video_pattern()
3537 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n"); in intel_dp_autotest_video_pattern()
3546 intel_dp->compliance.test_data.bpc = 6; in intel_dp_autotest_video_pattern()
3549 intel_dp->compliance.test_data.bpc = 8; in intel_dp_autotest_video_pattern()
3555 intel_dp->compliance.test_data.video_pattern = test_pattern; in intel_dp_autotest_video_pattern()
3556 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width); in intel_dp_autotest_video_pattern()
3557 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height); in intel_dp_autotest_video_pattern()
3559 intel_dp->compliance.test_active = true; in intel_dp_autotest_video_pattern()
3568 struct intel_connector *intel_connector = intel_dp->attached_connector; in intel_dp_autotest_edid()
3569 struct drm_connector *connector = &intel_connector->base; in intel_dp_autotest_edid()
3571 if (intel_connector->detect_edid == NULL || in intel_dp_autotest_edid()
3572 connector->edid_corrupt || in intel_dp_autotest_edid()
3573 intel_dp->aux.i2c_defer_count > 6) { in intel_dp_autotest_edid()
3581 if (intel_dp->aux.i2c_nack_count > 0 || in intel_dp_autotest_edid()
3582 intel_dp->aux.i2c_defer_count > 0) in intel_dp_autotest_edid()
3583 drm_dbg_kms(&i915->drm, in intel_dp_autotest_edid()
3585 intel_dp->aux.i2c_nack_count, in intel_dp_autotest_edid()
3586 intel_dp->aux.i2c_defer_count); in intel_dp_autotest_edid()
3587 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE; in intel_dp_autotest_edid()
3589 struct edid *block = intel_connector->detect_edid; in intel_dp_autotest_edid()
3594 block += intel_connector->detect_edid->extensions; in intel_dp_autotest_edid()
3596 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM, in intel_dp_autotest_edid()
3597 block->checksum) <= 0) in intel_dp_autotest_edid()
3598 drm_dbg_kms(&i915->drm, in intel_dp_autotest_edid()
3602 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED; in intel_dp_autotest_edid()
3606 intel_dp->compliance.test_active = true; in intel_dp_autotest_edid()
3615 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); in intel_dp_phy_pattern_update()
3617 &intel_dp->compliance.test_data.phytest; in intel_dp_phy_pattern_update()
3618 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dp_phy_pattern_update()
3619 enum pipe pipe = crtc->pipe; in intel_dp_phy_pattern_update()
3622 switch (data->phy_pattern) { in intel_dp_phy_pattern_update()
3624 drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n"); in intel_dp_phy_pattern_update()
3628 drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n"); in intel_dp_phy_pattern_update()
3633 drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n"); in intel_dp_phy_pattern_update()
3639 drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n"); in intel_dp_phy_pattern_update()
3646 * current firmware of DPR-100 could not set it, so hardcoding in intel_dp_phy_pattern_update()
3649 drm_dbg_kms(&dev_priv->drm, in intel_dp_phy_pattern_update()
3664 * current firmware of DPR-100 could not set it, so hardcoding in intel_dp_phy_pattern_update()
3667 drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n"); in intel_dp_phy_pattern_update()
3683 struct drm_device *dev = dig_port->base.base.dev; in intel_dp_autotest_phy_ddi_disable()
3685 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); in intel_dp_autotest_phy_ddi_disable()
3686 enum pipe pipe = crtc->pipe; in intel_dp_autotest_phy_ddi_disable()
3710 struct drm_device *dev = dig_port->base.base.dev; in intel_dp_autotest_phy_ddi_enable()
3712 enum port port = dig_port->base.port; in intel_dp_autotest_phy_ddi_enable()
3713 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); in intel_dp_autotest_phy_ddi_enable()
3714 enum pipe pipe = crtc->pipe; in intel_dp_autotest_phy_ddi_enable()
3738 &intel_dp->compliance.test_data.phytest; in intel_dp_process_phy_request()
3741 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, in intel_dp_process_phy_request()
3743 drm_dbg_kms(&i915->drm, "failed to get link status\n"); in intel_dp_process_phy_request()
3747 /* retrieve vswing & pre-emphasis setting */ in intel_dp_process_phy_request()
3759 drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, in intel_dp_process_phy_request()
3760 intel_dp->train_set, crtc_state->lane_count); in intel_dp_process_phy_request()
3762 drm_dp_set_phy_test_pattern(&intel_dp->aux, data, in intel_dp_process_phy_request()
3770 &intel_dp->compliance.test_data.phytest; in intel_dp_autotest_phy_pattern()
3772 if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) { in intel_dp_autotest_phy_pattern()
3773 drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n"); in intel_dp_autotest_phy_pattern()
3778 intel_dp->compliance.test_active = true; in intel_dp_autotest_phy_pattern()
3790 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request); in intel_dp_handle_test_request()
3792 drm_dbg_kms(&i915->drm, in intel_dp_handle_test_request()
3799 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n"); in intel_dp_handle_test_request()
3803 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n"); in intel_dp_handle_test_request()
3807 drm_dbg_kms(&i915->drm, "EDID test requested\n"); in intel_dp_handle_test_request()
3811 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n"); in intel_dp_handle_test_request()
3815 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n", in intel_dp_handle_test_request()
3821 intel_dp->compliance.test_type = request; in intel_dp_handle_test_request()
3824 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response); in intel_dp_handle_test_request()
3826 drm_dbg_kms(&i915->drm, in intel_dp_handle_test_request()
3833 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_dp_link_ok()
3834 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_dp_link_ok()
3835 bool uhbr = intel_dp->link_rate >= 1000000; in intel_dp_link_ok()
3840 intel_dp->lane_count); in intel_dp_link_ok()
3842 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count); in intel_dp_link_ok()
3848 drm_dbg_kms(&i915->drm, in intel_dp_link_ok()
3850 encoder->base.base.id, encoder->base.name, in intel_dp_link_ok()
3861 drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); in intel_dp_mst_hpd_irq()
3866 intel_hdcp_handle_cp_irq(intel_dp->attached_connector); in intel_dp_mst_hpd_irq()
3873 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_dp_mst_link_status()
3874 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_dp_mst_link_status()
3876 const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2; in intel_dp_mst_link_status()
3878 if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status, in intel_dp_mst_link_status()
3880 drm_err(&i915->drm, in intel_dp_mst_link_status()
3882 encoder->base.base.id, encoder->base.name); in intel_dp_mst_link_status()
3890 * intel_dp_check_mst_status - service any pending MST interrupts, check link status
3897 * - %true if pending interrupts were serviced (or no interrupts were
3899 * - %false if an error condition - like AUX failure or a loss of link - is
3908 drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0); in intel_dp_check_mst_status()
3915 drm_dbg_kms(&i915->drm, in intel_dp_check_mst_status()
3916 "failed to get ESI - device may have failed\n"); in intel_dp_check_mst_status()
3922 drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi); in intel_dp_check_mst_status()
3924 if (intel_dp->active_mst_links > 0 && link_ok && in intel_dp_check_mst_status()
3937 drm_dbg_kms(&i915->drm, "Failed to ack ESI\n"); in intel_dp_check_mst_status()
3949 is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux); in intel_dp_handle_hdmi_link_status_change()
3950 if (intel_dp->frl.is_trained && !is_active) { in intel_dp_handle_hdmi_link_status_change()
3951 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0) in intel_dp_handle_hdmi_link_status_change()
3955 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0) in intel_dp_handle_hdmi_link_status_change()
3958 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base); in intel_dp_handle_hdmi_link_status_change()
3960 intel_dp->frl.is_trained = false; in intel_dp_handle_hdmi_link_status_change()
3972 if (!intel_dp->link_trained) in intel_dp_needs_link_retrain()
3976 * While PSR source HW is enabled, it will control main-link sending in intel_dp_needs_link_retrain()
3986 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, in intel_dp_needs_link_retrain()
3991 * Validate the cached values of intel_dp->link_rate and in intel_dp_needs_link_retrain()
3992 * intel_dp->lane_count before attempting to retrain. in intel_dp_needs_link_retrain()
3998 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate, in intel_dp_needs_link_retrain()
3999 intel_dp->lane_count)) in intel_dp_needs_link_retrain()
4013 if (!conn_state->best_encoder) in intel_dp_has_connector()
4017 encoder = &dp_to_dig_port(intel_dp)->base; in intel_dp_has_connector()
4018 if (conn_state->best_encoder == &encoder->base) in intel_dp_has_connector()
4023 encoder = &intel_dp->mst_encoders[pipe]->base; in intel_dp_has_connector()
4024 if (conn_state->best_encoder == &encoder->base) in intel_dp_has_connector()
4045 drm_connector_list_iter_begin(&i915->drm, &conn_iter); in intel_dp_prep_link_retrain()
4048 connector->base.state; in intel_dp_prep_link_retrain()
4055 crtc = to_intel_crtc(conn_state->crtc); in intel_dp_prep_link_retrain()
4059 ret = drm_modeset_lock(&crtc->base.mutex, ctx); in intel_dp_prep_link_retrain()
4063 crtc_state = to_intel_crtc_state(crtc->base.state); in intel_dp_prep_link_retrain()
4065 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state)); in intel_dp_prep_link_retrain()
4067 if (!crtc_state->hw.active) in intel_dp_prep_link_retrain()
4070 if (conn_state->commit && in intel_dp_prep_link_retrain()
4071 !try_wait_for_completion(&conn_state->commit->hw_done)) in intel_dp_prep_link_retrain()
4074 *pipe_mask |= BIT(crtc->pipe); in intel_dp_prep_link_retrain()
4086 struct intel_connector *connector = intel_dp->attached_connector; in intel_dp_is_connected()
4088 return connector->base.status == connector_status_connected || in intel_dp_is_connected()
4089 intel_dp->is_mst; in intel_dp_is_connected()
4095 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dp_retrain_link()
4104 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, in intel_dp_retrain_link()
4116 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n", in intel_dp_retrain_link()
4117 encoder->base.base.id, encoder->base.name); in intel_dp_retrain_link()
4119 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { in intel_dp_retrain_link()
4121 to_intel_crtc_state(crtc->base.state); in intel_dp_retrain_link()
4123 /* Suppress underruns caused by re-training */ in intel_dp_retrain_link()
4124 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); in intel_dp_retrain_link()
4125 if (crtc_state->has_pch_encoder) in intel_dp_retrain_link()
4130 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { in intel_dp_retrain_link()
4132 to_intel_crtc_state(crtc->base.state); in intel_dp_retrain_link()
4147 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { in intel_dp_retrain_link()
4149 to_intel_crtc_state(crtc->base.state); in intel_dp_retrain_link()
4154 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); in intel_dp_retrain_link()
4155 if (crtc_state->has_pch_encoder) in intel_dp_retrain_link()
4174 drm_connector_list_iter_begin(&i915->drm, &conn_iter); in intel_dp_prep_phy_test()
4177 connector->base.state; in intel_dp_prep_phy_test()
4184 crtc = to_intel_crtc(conn_state->crtc); in intel_dp_prep_phy_test()
4188 ret = drm_modeset_lock(&crtc->base.mutex, ctx); in intel_dp_prep_phy_test()
4192 crtc_state = to_intel_crtc_state(crtc->base.state); in intel_dp_prep_phy_test()
4194 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state)); in intel_dp_prep_phy_test()
4196 if (!crtc_state->hw.active) in intel_dp_prep_phy_test()
4199 if (conn_state->commit && in intel_dp_prep_phy_test()
4200 !try_wait_for_completion(&conn_state->commit->hw_done)) in intel_dp_prep_phy_test()
4203 *pipe_mask |= BIT(crtc->pipe); in intel_dp_prep_phy_test()
4213 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dp_do_phy_test()
4219 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, in intel_dp_do_phy_test()
4231 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n", in intel_dp_do_phy_test()
4232 encoder->base.base.id, encoder->base.name); in intel_dp_do_phy_test()
4234 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { in intel_dp_do_phy_test()
4236 to_intel_crtc_state(crtc->base.state); in intel_dp_do_phy_test()
4261 if (ret == -EDEADLK) { in intel_dp_phy_test()
4271 drm_WARN(encoder->base.dev, ret, in intel_dp_phy_test()
4280 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in intel_dp_check_device_service_irq()
4283 if (drm_dp_dpcd_readb(&intel_dp->aux, in intel_dp_check_device_service_irq()
4287 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val); in intel_dp_check_device_service_irq()
4293 intel_hdcp_handle_cp_irq(intel_dp->attached_connector); in intel_dp_check_device_service_irq()
4296 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n"); in intel_dp_check_device_service_irq()
4303 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in intel_dp_check_link_service_irq()
4306 if (drm_dp_dpcd_readb(&intel_dp->aux, in intel_dp_check_link_service_irq()
4310 if (drm_dp_dpcd_writeb(&intel_dp->aux, in intel_dp_check_link_service_irq()
4324 * 4. Check link status on receipt of hot-plug interrupt
4326 * intel_dp_short_pulse - handles short pulse interrupts
4335 u8 old_sink_count = intel_dp->sink_count; in intel_dp_short_pulse()
4342 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); in intel_dp_short_pulse()
4352 if ((old_sink_count != intel_dp->sink_count) || !ret) { in intel_dp_short_pulse()
4361 drm_dp_cec_irq(&intel_dp->aux); in intel_dp_short_pulse()
4369 switch (intel_dp->compliance.test_type) { in intel_dp_short_pulse()
4371 drm_dbg_kms(&dev_priv->drm, in intel_dp_short_pulse()
4374 drm_kms_helper_hotplug_event(&dev_priv->drm); in intel_dp_short_pulse()
4377 drm_dbg_kms(&dev_priv->drm, in intel_dp_short_pulse()
4382 * FIXME get rid of the ad-hoc phy test modeset code in intel_dp_short_pulse()
4397 u8 *dpcd = intel_dp->dpcd; in intel_dp_detect_dpcd()
4400 if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp))) in intel_dp_detect_dpcd()
4412 /* If we're HPD-aware, SINK_COUNT changes dynamically */ in intel_dp_detect_dpcd()
4414 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { in intel_dp_detect_dpcd()
4415 return intel_dp->sink_count ? in intel_dp_detect_dpcd()
4423 if (drm_probe_ddc(&intel_dp->aux.ddc)) in intel_dp_detect_dpcd()
4427 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { in intel_dp_detect_dpcd()
4428 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; in intel_dp_detect_dpcd()
4433 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & in intel_dp_detect_dpcd()
4441 drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n"); in intel_dp_detect_dpcd()
4452 * intel_digital_port_connected - is the specified port connected?
4457 * pretty much treat the port as disconnected. This is relevant for type-C
4464 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_digital_port_connected()
4470 is_connected = dig_port->connected(encoder); in intel_digital_port_connected()
4478 struct intel_connector *intel_connector = intel_dp->attached_connector; in intel_dp_get_edid()
4481 if (intel_connector->edid) { in intel_dp_get_edid()
4483 if (IS_ERR(intel_connector->edid)) in intel_dp_get_edid()
4486 return drm_edid_duplicate(intel_connector->edid); in intel_dp_get_edid()
4488 return drm_get_edid(&intel_connector->base, in intel_dp_get_edid()
4489 &intel_dp->aux.ddc); in intel_dp_get_edid()
4497 struct intel_connector *connector = intel_dp->attached_connector; in intel_dp_update_dfp()
4499 intel_dp->dfp.max_bpc = in intel_dp_update_dfp()
4500 drm_dp_downstream_max_bpc(intel_dp->dpcd, in intel_dp_update_dfp()
4501 intel_dp->downstream_ports, edid); in intel_dp_update_dfp()
4503 intel_dp->dfp.max_dotclock = in intel_dp_update_dfp()
4504 drm_dp_downstream_max_dotclock(intel_dp->dpcd, in intel_dp_update_dfp()
4505 intel_dp->downstream_ports); in intel_dp_update_dfp()
4507 intel_dp->dfp.min_tmds_clock = in intel_dp_update_dfp()
4508 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd, in intel_dp_update_dfp()
4509 intel_dp->downstream_ports, in intel_dp_update_dfp()
4511 intel_dp->dfp.max_tmds_clock = in intel_dp_update_dfp()
4512 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd, in intel_dp_update_dfp()
4513 intel_dp->downstream_ports, in intel_dp_update_dfp()
4516 intel_dp->dfp.pcon_max_frl_bw = in intel_dp_update_dfp()
4517 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd, in intel_dp_update_dfp()
4518 intel_dp->downstream_ports); in intel_dp_update_dfp()
4520 drm_dbg_kms(&i915->drm, in intel_dp_update_dfp()
4521 … "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n", in intel_dp_update_dfp()
4522 connector->base.base.id, connector->base.name, in intel_dp_update_dfp()
4523 intel_dp->dfp.max_bpc, in intel_dp_update_dfp()
4524 intel_dp->dfp.max_dotclock, in intel_dp_update_dfp()
4525 intel_dp->dfp.min_tmds_clock, in intel_dp_update_dfp()
4526 intel_dp->dfp.max_tmds_clock, in intel_dp_update_dfp()
4527 intel_dp->dfp.pcon_max_frl_bw); in intel_dp_update_dfp()
4536 struct intel_connector *connector = intel_dp->attached_connector; in intel_dp_update_420()
4550 is_branch = drm_dp_is_branch(intel_dp->dpcd); in intel_dp_update_420()
4552 drm_dp_downstream_420_passthrough(intel_dp->dpcd, in intel_dp_update_420()
4553 intel_dp->downstream_ports); in intel_dp_update_420()
4554 /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */ in intel_dp_update_420()
4556 dp_to_dig_port(intel_dp)->lspcon.active || in intel_dp_update_420()
4557 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd, in intel_dp_update_420()
4558 intel_dp->downstream_ports); in intel_dp_update_420()
4559 rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd, in intel_dp_update_420()
4560 intel_dp->downstream_ports, in intel_dp_update_420()
4564 /* Let PCON convert from RGB->YCbCr if possible */ in intel_dp_update_420()
4566 intel_dp->dfp.rgb_to_ycbcr = true; in intel_dp_update_420()
4567 intel_dp->dfp.ycbcr_444_to_420 = true; in intel_dp_update_420()
4568 connector->base.ycbcr_420_allowed = true; in intel_dp_update_420()
4570 /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */ in intel_dp_update_420()
4571 intel_dp->dfp.ycbcr_444_to_420 = in intel_dp_update_420()
4574 connector->base.ycbcr_420_allowed = in intel_dp_update_420()
4578 /* 4:4:4->4:2:0 conversion is the only way */ in intel_dp_update_420()
4579 intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420; in intel_dp_update_420()
4581 connector->base.ycbcr_420_allowed = ycbcr_444_to_420; in intel_dp_update_420()
4584 drm_dbg_kms(&i915->drm, in intel_dp_update_420()
4585 …"[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversi… in intel_dp_update_420()
4586 connector->base.base.id, connector->base.name, in intel_dp_update_420()
4587 str_yes_no(intel_dp->dfp.rgb_to_ycbcr), in intel_dp_update_420()
4588 str_yes_no(connector->base.ycbcr_420_allowed), in intel_dp_update_420()
4589 str_yes_no(intel_dp->dfp.ycbcr_444_to_420)); in intel_dp_update_420()
4596 struct intel_connector *connector = intel_dp->attached_connector; in intel_dp_set_edid()
4602 connector->detect_edid = edid; in intel_dp_set_edid()
4605 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n", in intel_dp_set_edid()
4606 connector->base.base.id, connector->base.name, str_yes_no(vrr_capable)); in intel_dp_set_edid()
4607 drm_connector_set_vrr_capable_property(&connector->base, vrr_capable); in intel_dp_set_edid()
4612 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { in intel_dp_set_edid()
4613 intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid); in intel_dp_set_edid()
4614 intel_dp->has_audio = drm_detect_monitor_audio(edid); in intel_dp_set_edid()
4617 drm_dp_cec_set_edid(&intel_dp->aux, edid); in intel_dp_set_edid()
4623 struct intel_connector *connector = intel_dp->attached_connector; in intel_dp_unset_edid()
4625 drm_dp_cec_unset_edid(&intel_dp->aux); in intel_dp_unset_edid()
4626 kfree(connector->detect_edid); in intel_dp_unset_edid()
4627 connector->detect_edid = NULL; in intel_dp_unset_edid()
4629 intel_dp->has_hdmi_sink = false; in intel_dp_unset_edid()
4630 intel_dp->has_audio = false; in intel_dp_unset_edid()
4632 intel_dp->dfp.max_bpc = 0; in intel_dp_unset_edid()
4633 intel_dp->dfp.max_dotclock = 0; in intel_dp_unset_edid()
4634 intel_dp->dfp.min_tmds_clock = 0; in intel_dp_unset_edid()
4635 intel_dp->dfp.max_tmds_clock = 0; in intel_dp_unset_edid()
4637 intel_dp->dfp.pcon_max_frl_bw = 0; in intel_dp_unset_edid()
4639 intel_dp->dfp.ycbcr_444_to_420 = false; in intel_dp_unset_edid()
4640 connector->base.ycbcr_420_allowed = false; in intel_dp_unset_edid()
4642 drm_connector_set_vrr_capable_property(&connector->base, in intel_dp_unset_edid()
4651 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_dp_detect()
4654 struct intel_encoder *encoder = &dig_port->base; in intel_dp_detect()
4657 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", in intel_dp_detect()
4658 connector->base.id, connector->name); in intel_dp_detect()
4659 drm_WARN_ON(&dev_priv->drm, in intel_dp_detect()
4660 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); in intel_dp_detect()
4674 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); in intel_dp_detect()
4675 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); in intel_dp_detect()
4677 if (intel_dp->is_mst) { in intel_dp_detect()
4678 drm_dbg_kms(&dev_priv->drm, in intel_dp_detect()
4680 intel_dp->is_mst, in intel_dp_detect()
4681 intel_dp->mst_mgr.mst_state); in intel_dp_detect()
4682 intel_dp->is_mst = false; in intel_dp_detect()
4683 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, in intel_dp_detect()
4684 intel_dp->is_mst); in intel_dp_detect()
4700 if (intel_dp->reset_link_params || intel_dp->is_mst) { in intel_dp_detect()
4702 intel_dp->reset_link_params = false; in intel_dp_detect()
4707 if (intel_dp->is_mst) { in intel_dp_detect()
4734 intel_dp->aux.i2c_nack_count = 0; in intel_dp_detect()
4735 intel_dp->aux.i2c_defer_count = 0; in intel_dp_detect()
4739 to_intel_connector(connector)->detect_edid) in intel_dp_detect()
4745 if (status != connector_status_connected && !intel_dp->is_mst) in intel_dp_detect()
4757 intel_dp->dpcd, in intel_dp_detect()
4758 intel_dp->downstream_ports); in intel_dp_detect()
4767 struct intel_encoder *intel_encoder = &dig_port->base; in intel_dp_force()
4768 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); in intel_dp_force()
4773 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", in intel_dp_force()
4774 connector->base.id, connector->name); in intel_dp_force()
4777 if (connector->status != connector_status_connected) in intel_dp_force()
4793 edid = intel_connector->detect_edid; in intel_dp_get_modes()
4808 mode = drm_dp_downstream_mode(connector->dev, in intel_dp_get_modes()
4809 intel_dp->dpcd, in intel_dp_get_modes()
4810 intel_dp->downstream_ports); in intel_dp_get_modes()
4823 struct drm_i915_private *i915 = to_i915(connector->dev); in intel_dp_connector_register()
4826 struct intel_lspcon *lspcon = &dig_port->lspcon; in intel_dp_connector_register()
4833 drm_dbg_kms(&i915->drm, "registering %s bus for %s\n", in intel_dp_connector_register()
4834 intel_dp->aux.name, connector->kdev->kobj.name); in intel_dp_connector_register()
4836 intel_dp->aux.dev = connector->kdev; in intel_dp_connector_register()
4837 ret = drm_dp_aux_register(&intel_dp->aux); in intel_dp_connector_register()
4839 drm_dp_cec_register_connector(&intel_dp->aux, connector); in intel_dp_connector_register()
4841 if (!intel_bios_is_lspcon_present(i915, dig_port->base.port)) in intel_dp_connector_register()
4850 if (lspcon->hdr_supported) in intel_dp_connector_register()
4862 drm_dp_cec_unregister_connector(&intel_dp->aux); in intel_dp_connector_unregister()
4863 drm_dp_aux_unregister(&intel_dp->aux); in intel_dp_connector_unregister()
4870 struct intel_dp *intel_dp = &dig_port->dp; in intel_dp_encoder_flush_work()
4896 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_modeset_tile_group()
4901 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); in intel_modeset_tile_group()
4907 if (!connector->has_tile || in intel_modeset_tile_group()
4908 connector->tile_group->id != tile_group_id) in intel_modeset_tile_group()
4911 conn_state = drm_atomic_get_connector_state(&state->base, in intel_modeset_tile_group()
4918 crtc = to_intel_crtc(conn_state->crtc); in intel_modeset_tile_group()
4924 crtc_state->uapi.mode_changed = true; in intel_modeset_tile_group()
4926 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); in intel_modeset_tile_group()
4937 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_modeset_affected_transcoders()
4943 for_each_intel_crtc(&dev_priv->drm, crtc) { in intel_modeset_affected_transcoders()
4947 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); in intel_modeset_affected_transcoders()
4951 if (!crtc_state->hw.enable) in intel_modeset_affected_transcoders()
4954 if (!(transcoders & BIT(crtc_state->cpu_transcoder))) in intel_modeset_affected_transcoders()
4957 crtc_state->uapi.mode_changed = true; in intel_modeset_affected_transcoders()
4959 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); in intel_modeset_affected_transcoders()
4963 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); in intel_modeset_affected_transcoders()
4967 transcoders &= ~BIT(crtc_state->cpu_transcoder); in intel_modeset_affected_transcoders()
4970 drm_WARN_ON(&dev_priv->drm, transcoders != 0); in intel_modeset_affected_transcoders()
4979 drm_atomic_get_old_connector_state(&state->base, connector); in intel_modeset_synced_crtcs()
4984 crtc = to_intel_crtc(old_conn_state->crtc); in intel_modeset_synced_crtcs()
4990 if (!old_crtc_state->hw.active) in intel_modeset_synced_crtcs()
4993 transcoders = old_crtc_state->sync_mode_slaves_mask; in intel_modeset_synced_crtcs()
4994 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER) in intel_modeset_synced_crtcs()
4995 transcoders |= BIT(old_crtc_state->master_transcoder); in intel_modeset_synced_crtcs()
5004 struct drm_i915_private *dev_priv = to_i915(conn->dev); in intel_dp_connector_atomic_check()
5008 struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder); in intel_dp_connector_atomic_check()
5011 ret = intel_digital_connector_atomic_check(conn, &state->base); in intel_dp_connector_atomic_check()
5016 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr); in intel_dp_connector_atomic_check()
5031 if (conn->has_tile) { in intel_dp_connector_atomic_check()
5032 ret = intel_modeset_tile_group(state, conn->tile_group->id); in intel_dp_connector_atomic_check()
5043 struct drm_i915_private *i915 = to_i915(connector->dev); in intel_dp_oob_hotplug_event()
5045 spin_lock_irq(&i915->irq_lock); in intel_dp_oob_hotplug_event()
5046 i915->display.hotplug.event_bits |= BIT(encoder->hpd_pin); in intel_dp_oob_hotplug_event()
5047 spin_unlock_irq(&i915->irq_lock); in intel_dp_oob_hotplug_event()
5048 queue_delayed_work(system_wq, &i915->display.hotplug.hotplug_work, 0); in intel_dp_oob_hotplug_event()
5074 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_dp_hpd_pulse()
5075 struct intel_dp *intel_dp = &dig_port->dp; in intel_dp_hpd_pulse()
5077 if (dig_port->base.type == INTEL_OUTPUT_EDP && in intel_dp_hpd_pulse()
5083 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..." in intel_dp_hpd_pulse()
5085 drm_dbg_kms(&i915->drm, in intel_dp_hpd_pulse()
5088 dig_port->base.base.base.id, in intel_dp_hpd_pulse()
5089 dig_port->base.base.name); in intel_dp_hpd_pulse()
5093 drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n", in intel_dp_hpd_pulse()
5094 dig_port->base.base.base.id, in intel_dp_hpd_pulse()
5095 dig_port->base.base.name, in intel_dp_hpd_pulse()
5099 intel_dp->reset_link_params = true; in intel_dp_hpd_pulse()
5103 if (intel_dp->is_mst) { in intel_dp_hpd_pulse()
5151 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_dp_add_properties()
5152 enum port port = dp_to_dig_port(intel_dp)->base.port; in intel_dp_add_properties()
5166 /* Register HDMI colorspace for case of lspcon */ in intel_dp_add_properties()
5186 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; in intel_dp_add_properties()
5197 struct intel_connector *connector = intel_dp->attached_connector; in intel_edp_add_properties()
5198 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_edp_add_properties()
5205 drm_connector_set_panel_orientation_with_quirk(&connector->base, in intel_edp_add_properties()
5206 i915->display.vbt.orientation, in intel_edp_add_properties()
5207 fixed_mode->hdisplay, in intel_edp_add_properties()
5208 fixed_mode->vdisplay); in intel_edp_add_properties()
5215 struct drm_device *dev = &dev_priv->drm; in intel_edp_init_connector()
5216 struct drm_connector *connector = &intel_connector->base; in intel_edp_init_connector()
5218 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_edp_init_connector()
5230 * with an already powered-on LVDS power sequencer. in intel_edp_init_connector()
5235 drm_info(&dev_priv->drm, in intel_edp_init_connector()
5248 drm_info(&dev_priv->drm, in intel_edp_init_connector()
5253 mutex_lock(&dev->mode_config.mutex); in intel_edp_init_connector()
5254 edid = drm_get_edid(connector, &intel_dp->aux.ddc); in intel_edp_init_connector()
5259 drm_dbg_kms(&dev_priv->drm, in intel_edp_init_connector()
5261 connector->base.id, connector->name); in intel_edp_init_connector()
5268 edid = ERR_PTR(-EINVAL); in intel_edp_init_connector()
5271 edid = ERR_PTR(-ENOENT); in intel_edp_init_connector()
5273 intel_connector->edid = edid; in intel_edp_init_connector()
5275 intel_bios_init_panel(dev_priv, &intel_connector->panel, in intel_edp_init_connector()
5276 encoder->devdata, IS_ERR(edid) ? NULL : edid); in intel_edp_init_connector()
5279 intel_connector->panel.vbt.drrs_type != DRRS_TYPE_NONE || in intel_edp_init_connector()
5286 list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head) in intel_edp_init_connector()
5293 mutex_unlock(&dev->mode_config.mutex); in intel_edp_init_connector()
5304 pipe = intel_dp->pps.pps_pipe; in intel_edp_init_connector()
5309 drm_dbg_kms(&dev_priv->drm, in intel_edp_init_connector()
5337 connector = &intel_connector->base; in intel_dp_modeset_retry_work_fn()
5338 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id, in intel_dp_modeset_retry_work_fn()
5339 connector->name); in intel_dp_modeset_retry_work_fn()
5342 mutex_lock(&connector->dev->mode_config.mutex); in intel_dp_modeset_retry_work_fn()
5348 mutex_unlock(&connector->dev->mode_config.mutex); in intel_dp_modeset_retry_work_fn()
5357 struct drm_connector *connector = &intel_connector->base; in intel_dp_init_connector()
5358 struct intel_dp *intel_dp = &dig_port->dp; in intel_dp_init_connector()
5359 struct intel_encoder *intel_encoder = &dig_port->base; in intel_dp_init_connector()
5360 struct drm_device *dev = intel_encoder->base.dev; in intel_dp_init_connector()
5362 enum port port = intel_encoder->port; in intel_dp_init_connector()
5367 INIT_WORK(&intel_connector->modeset_retry_work, in intel_dp_init_connector()
5370 if (drm_WARN(dev, dig_port->max_lanes < 1, in intel_dp_init_connector()
5372 dig_port->max_lanes, intel_encoder->base.base.id, in intel_dp_init_connector()
5373 intel_encoder->base.name)) in intel_dp_init_connector()
5376 intel_dp->reset_link_params = true; in intel_dp_init_connector()
5377 intel_dp->pps.pps_pipe = INVALID_PIPE; in intel_dp_init_connector()
5378 intel_dp->pps.active_pipe = INVALID_PIPE; in intel_dp_init_connector()
5381 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg); in intel_dp_init_connector()
5382 intel_dp->attached_connector = intel_connector; in intel_dp_init_connector()
5391 intel_encoder->type = INTEL_OUTPUT_EDP; in intel_dp_init_connector()
5406 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp); in intel_dp_init_connector()
5408 drm_dbg_kms(&dev_priv->drm, in intel_dp_init_connector()
5411 intel_encoder->base.base.id, intel_encoder->base.name); in intel_dp_init_connector()
5417 connector->interlace_allowed = true; in intel_dp_init_connector()
5418 connector->doublescan_allowed = 0; in intel_dp_init_connector()
5420 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; in intel_dp_init_connector()
5427 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; in intel_dp_init_connector()
5429 intel_connector->get_hw_state = intel_connector_get_hw_state; in intel_dp_init_connector()
5442 intel_connector->base.base.id); in intel_dp_init_connector()
5449 drm_dbg_kms(&dev_priv->drm, in intel_dp_init_connector()
5463 intel_dp->frl.is_trained = false; in intel_dp_init_connector()
5464 intel_dp->frl.trained_rate_gbps = 0; in intel_dp_init_connector()
5483 for_each_intel_encoder(&dev_priv->drm, encoder) { in intel_dp_mst_suspend()
5486 if (encoder->type != INTEL_OUTPUT_DDI) in intel_dp_mst_suspend()
5494 if (intel_dp->is_mst) in intel_dp_mst_suspend()
5495 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr); in intel_dp_mst_suspend()
5506 for_each_intel_encoder(&dev_priv->drm, encoder) { in intel_dp_mst_resume()
5510 if (encoder->type != INTEL_OUTPUT_DDI) in intel_dp_mst_resume()
5518 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr, in intel_dp_mst_resume()
5521 intel_dp->is_mst = false; in intel_dp_mst_resume()
5522 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, in intel_dp_mst_resume()