Lines Matching +full:0 +full:x5ffff
12 #define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0
14 #define _ADLP_PIPEDMC_REG_MMIO_BASE_A 0x5f000
15 #define _TGL_PIPEDMC_REG_MMIO_BASE_A 0x92000
20 0x400 * ((dmc_id) - 1))
22 #define __DMC_REG_MMIO_BASE 0x8f000
33 #define _DMC_EVT_HTP_0 0x8f004
38 #define _DMC_EVT_CTL_0 0x8f034
46 #define DMC_EVT_CTL_TYPE_LEVEL_0 0
52 #define DMC_EVT_CTL_EVENT_ID_FALSE 0x01
54 #define DMC_EVT_CTL_EVENT_ID_CLK_MSEC 0xbf
56 #define DMC_HTP_ADDR_SKL 0x00500034
57 #define DMC_SSP_BASE _MMIO(0x8F074)
58 #define DMC_HTP_SKL _MMIO(0x8F004)
59 #define DMC_LAST_WRITE _MMIO(0x8F034)
60 #define DMC_LAST_WRITE_VALUE 0xc003b400
61 #define DMC_MMIO_START_RANGE 0x80000
62 #define DMC_MMIO_END_RANGE 0x8FFFF
63 #define DMC_V1_MMIO_START_RANGE 0x80000
64 #define TGL_MAIN_MMIO_START 0x8F000
65 #define TGL_MAIN_MMIO_END 0x8FFFF
66 #define _TGL_PIPEA_MMIO_START 0x92000
67 #define _TGL_PIPEA_MMIO_END 0x93FFF
68 #define _TGL_PIPEB_MMIO_START 0x96000
69 #define _TGL_PIPEB_MMIO_END 0x97FFF
70 #define ADLP_PIPE_MMIO_START 0x5F000
71 #define ADLP_PIPE_MMIO_END 0x5FFFF
79 #define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030)
80 #define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C)
81 #define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038)
82 #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
83 #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
84 #define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154)
86 #define TGL_DMC_DEBUG3 _MMIO(0x101090)
87 #define DG1_DMC_DEBUG3 _MMIO(0x13415c)