Lines Matching refs:i915
251 static bool has_dmc_id_fw(struct drm_i915_private *i915, int dmc_id) in has_dmc_id_fw() argument
253 return i915->display.dmc.dmc_info[dmc_id].payload; in has_dmc_id_fw()
256 bool intel_dmc_has_payload(struct drm_i915_private *i915) in intel_dmc_has_payload() argument
258 return has_dmc_id_fw(i915, DMC_FW_MAIN); in intel_dmc_has_payload()
262 intel_get_stepping_info(struct drm_i915_private *i915, in intel_get_stepping_info() argument
265 const char *step_name = intel_step_name(RUNTIME_INFO(i915)->step.display_step); in intel_get_stepping_info()
280 static void disable_event_handler(struct drm_i915_private *i915, in disable_event_handler() argument
283 intel_de_write(i915, ctl_reg, in disable_event_handler()
288 intel_de_write(i915, htp_reg, 0); in disable_event_handler()
292 disable_flip_queue_event(struct drm_i915_private *i915, in disable_flip_queue_event() argument
298 event_ctl = intel_de_read(i915, ctl_reg); in disable_flip_queue_event()
299 event_htp = intel_de_read(i915, htp_reg); in disable_flip_queue_event()
307 drm_dbg_kms(&i915->drm, in disable_flip_queue_event()
313 disable_event_handler(i915, ctl_reg, htp_reg); in disable_flip_queue_event()
317 get_flip_queue_event_regs(struct drm_i915_private *i915, int dmc_id, in get_flip_queue_event_regs() argument
322 if (DISPLAY_VER(i915) == 12) { in get_flip_queue_event_regs()
323 *ctl_reg = DMC_EVT_CTL(i915, dmc_id, 3); in get_flip_queue_event_regs()
324 *htp_reg = DMC_EVT_HTP(i915, dmc_id, 3); in get_flip_queue_event_regs()
330 if (IS_DG2(i915)) { in get_flip_queue_event_regs()
331 *ctl_reg = DMC_EVT_CTL(i915, dmc_id, 2); in get_flip_queue_event_regs()
332 *htp_reg = DMC_EVT_HTP(i915, dmc_id, 2); in get_flip_queue_event_regs()
343 disable_all_flip_queue_events(struct drm_i915_private *i915) in disable_all_flip_queue_events() argument
348 if (!IS_DG2(i915) && !IS_TIGERLAKE(i915)) in disable_all_flip_queue_events()
355 if (!has_dmc_id_fw(i915, dmc_id)) in disable_all_flip_queue_events()
358 if (!get_flip_queue_event_regs(i915, dmc_id, &ctl_reg, &htp_reg)) in disable_all_flip_queue_events()
361 disable_flip_queue_event(i915, ctl_reg, htp_reg); in disable_all_flip_queue_events()
365 static void disable_all_event_handlers(struct drm_i915_private *i915) in disable_all_event_handlers() argument
370 if (DISPLAY_VER(i915) < 12) in disable_all_event_handlers()
376 if (!has_dmc_id_fw(i915, id)) in disable_all_event_handlers()
380 disable_event_handler(i915, in disable_all_event_handlers()
381 DMC_EVT_CTL(i915, id, handler), in disable_all_event_handlers()
382 DMC_EVT_HTP(i915, id, handler)); in disable_all_event_handlers()
386 static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) in pipedmc_clock_gating_wa() argument
390 if (DISPLAY_VER(i915) != 13) in pipedmc_clock_gating_wa()
402 intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe), in pipedmc_clock_gating_wa()
406 intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe), in pipedmc_clock_gating_wa()
472 void intel_dmc_disable_program(struct drm_i915_private *i915) in intel_dmc_disable_program() argument
474 if (!intel_dmc_has_payload(i915)) in intel_dmc_disable_program()
477 pipedmc_clock_gating_wa(i915, true); in intel_dmc_disable_program()
478 disable_all_event_handlers(i915); in intel_dmc_disable_program()
479 pipedmc_clock_gating_wa(i915, false); in intel_dmc_disable_program()
482 void assert_dmc_loaded(struct drm_i915_private *i915) in assert_dmc_loaded() argument
484 drm_WARN_ONCE(&i915->drm, in assert_dmc_loaded()
485 … !intel_de_read(i915, DMC_PROGRAM(i915->display.dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)), in assert_dmc_loaded()
487 drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE), in assert_dmc_loaded()
489 drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_HTP_SKL), in assert_dmc_loaded()
522 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc); in dmc_set_fw_offset() local
528 drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", id); in dmc_set_fw_offset()
550 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc); in dmc_mmio_addr_sanity_check() local
555 drm_warn(&i915->drm, "Unsupported firmware id %u\n", dmc_id); in dmc_mmio_addr_sanity_check()
565 } else if (DISPLAY_VER(i915) >= 13) { in dmc_mmio_addr_sanity_check()
568 } else if (DISPLAY_VER(i915) >= 12) { in dmc_mmio_addr_sanity_check()
572 drm_warn(&i915->drm, "Unknown mmio range for sanity check"); in dmc_mmio_addr_sanity_check()
588 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc); in parse_dmc_fw_header() local
636 drm_err(&i915->drm, "Unknown DMC fw header version: %u\n", in parse_dmc_fw_header()
642 drm_err(&i915->drm, "DMC firmware has wrong dmc header length " in parse_dmc_fw_header()
649 drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); in parse_dmc_fw_header()
655 drm_err(&i915->drm, "DMC firmware has Wrong MMIO Addresses\n"); in parse_dmc_fw_header()
674 drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size); in parse_dmc_fw_header()
689 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); in parse_dmc_fw_header()
699 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc); in parse_dmc_fw_package() local
712 drm_err(&i915->drm, "DMC firmware has unknown header version %u\n", in parse_dmc_fw_package()
726 drm_err(&i915->drm, "DMC firmware has wrong package header length " in parse_dmc_fw_package()
744 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); in parse_dmc_fw_package()
753 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc); in parse_dmc_fw_css() local
756 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); in parse_dmc_fw_css()
762 drm_err(&i915->drm, "DMC firmware has wrong CSS header length " in parse_dmc_fw_css()
770 drm_info(&i915->drm, "Refusing to load DMC firmware v%u.%u," in parse_dmc_fw_css()
1037 struct drm_i915_private *i915) in intel_dmc_print_error_state() argument
1039 struct intel_dmc *dmc = &i915->display.dmc; in intel_dmc_print_error_state()
1041 if (!HAS_DMC(i915)) in intel_dmc_print_error_state()
1045 str_yes_no(intel_dmc_has_payload(i915))); in intel_dmc_print_error_state()
1053 struct drm_i915_private *i915 = m->private; in intel_dmc_debugfs_status_show() local
1058 if (!HAS_DMC(i915)) in intel_dmc_debugfs_status_show()
1061 dmc = &i915->display.dmc; in intel_dmc_debugfs_status_show()
1063 wakeref = intel_runtime_pm_get(&i915->runtime_pm); in intel_dmc_debugfs_status_show()
1066 str_yes_no(intel_dmc_has_payload(i915))); in intel_dmc_debugfs_status_show()
1069 str_yes_no(GRAPHICS_VER(i915) >= 12)); in intel_dmc_debugfs_status_show()
1073 str_yes_no(IS_ALDERLAKE_P(i915))); in intel_dmc_debugfs_status_show()
1077 if (!intel_dmc_has_payload(i915)) in intel_dmc_debugfs_status_show()
1083 if (DISPLAY_VER(i915) >= 12) { in intel_dmc_debugfs_status_show()
1084 if (IS_DGFX(i915)) { in intel_dmc_debugfs_status_show()
1098 intel_de_read(i915, IS_DGFX(i915) ? in intel_dmc_debugfs_status_show()
1101 dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT : in intel_dmc_debugfs_status_show()
1103 if (!IS_GEMINILAKE(i915) && !IS_BROXTON(i915)) in intel_dmc_debugfs_status_show()
1107 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(i915, dc5_reg)); in intel_dmc_debugfs_status_show()
1110 intel_de_read(i915, dc6_reg)); in intel_dmc_debugfs_status_show()
1114 intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); in intel_dmc_debugfs_status_show()
1116 intel_de_read(i915, DMC_SSP_BASE)); in intel_dmc_debugfs_status_show()
1117 seq_printf(m, "htp: 0x%08x\n", intel_de_read(i915, DMC_HTP_SKL)); in intel_dmc_debugfs_status_show()
1119 intel_runtime_pm_put(&i915->runtime_pm, wakeref); in intel_dmc_debugfs_status_show()
1126 void intel_dmc_debugfs_register(struct drm_i915_private *i915) in intel_dmc_debugfs_register() argument
1128 struct drm_minor *minor = i915->drm.primary; in intel_dmc_debugfs_register()
1131 i915, &intel_dmc_debugfs_status_fops); in intel_dmc_debugfs_register()