3042 		if (crtc_state->dither && crtc_state->pipe_bpp != 30)  in i9xx_set_pipeconf()
3046 		switch (crtc_state->pipe_bpp) {  in i9xx_set_pipeconf()
3049 			MISSING_CASE(crtc_state->pipe_bpp);  in i9xx_set_pipeconf()
3249 			pipe_config->pipe_bpp = 18;  in i9xx_get_pipe_config()
3252 			pipe_config->pipe_bpp = 24;  in i9xx_get_pipe_config()
3255 			pipe_config->pipe_bpp = 30;  in i9xx_get_pipe_config()
3359 	switch (crtc_state->pipe_bpp) {  in ilk_set_pipeconf()
3362 		MISSING_CASE(crtc_state->pipe_bpp);  in ilk_set_pipeconf()
3445 	switch (crtc_state->pipe_bpp) {  in bdw_set_pipemisc()
3461 		MISSING_CASE(crtc_state->pipe_bpp);  in bdw_set_pipemisc()
3667 		pipe_config->pipe_bpp = 18;  in ilk_get_pipe_config()
3670 		pipe_config->pipe_bpp = 24;  in ilk_get_pipe_config()
3673 		pipe_config->pipe_bpp = 30;  in ilk_get_pipe_config()
3676 		pipe_config->pipe_bpp = 36;  in ilk_get_pipe_config()
4519 	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)  in intel_crtc_dotclock()
4521 					     pipe_config->pipe_bpp);  in intel_crtc_dotclock()
4937 	if (bpp < crtc_state->pipe_bpp) {  in compute_sink_pipe_bpp()
4944 			    crtc_state->pipe_bpp);  in compute_sink_pipe_bpp()
4946 		crtc_state->pipe_bpp = bpp;  in compute_sink_pipe_bpp()
4971 	crtc_state->pipe_bpp = bpp;  in compute_baseline_pipe_bpp()
5241 	base_bpp = crtc_state->pipe_bpp;  in intel_modeset_pipe_config()
5343 	crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&  in intel_modeset_pipe_config()
5348 		    base_bpp, crtc_state->pipe_bpp, crtc_state->dither);  in intel_modeset_pipe_config()
5875 		PIPE_CONF_CHECK_I(pipe_bpp);  in intel_pipe_config_compare()