433 		if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder),  in intel_wait_for_pipe_off()
455 		u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));  in assert_transcoder()
568 	reg = PIPECONF(cpu_transcoder);  in intel_enable_transcoder()
607 	reg = PIPECONF(cpu_transcoder);  in intel_disable_transcoder()
2938 		return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;  in intel_pipe_is_interlaced()
2940 		return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;  in intel_pipe_is_interlaced()
3081 	intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);  in i9xx_set_pipeconf()
3082 	intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));  in i9xx_set_pipeconf()
3241 	tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));  in i9xx_get_pipe_config()
3405 	intel_de_write(dev_priv, PIPECONF(pipe), val);  in ilk_set_pipeconf()
3406 	intel_de_posting_read(dev_priv, PIPECONF(pipe));  in ilk_set_pipeconf()
3435 	intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);  in hsw_set_transconf()
3436 	intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder));  in hsw_set_transconf()
3661 	tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));  in ilk_get_pipe_config()
3976 	tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));  in hsw_get_transcoder_state()
4083 					PIPECONF(pipe_config->cpu_transcoder));  in hsw_get_pipe_config()
8885 	intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE);  in i830_enable_pipe()
8886 	intel_de_posting_read(dev_priv, PIPECONF(pipe));  in i830_enable_pipe()
8909 	intel_de_write(dev_priv, PIPECONF(pipe), 0);  in i830_disable_pipe()
8910 	intel_de_posting_read(dev_priv, PIPECONF(pipe));  in i830_disable_pipe()