671 	if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)  in intel_ddi_connector_get_hw_state()
738 	if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {  in intel_ddi_get_encoder_pipes()
987 	if (encoder->port == PORT_A && dig_port->max_lanes == 4)  in skl_ddi_set_iboost()
1777 	case PORT_A:  in bxt_ddi_get_pll()
2422 			    is_mst && (port == PORT_A || port == PORT_E));  in hsw_ddi_pre_enable_dp()
2424 		drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);  in hsw_ddi_pre_enable_dp()
2462 	if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) &&  in hsw_ddi_pre_enable_dp()
2795 	if (port == PORT_A && DISPLAY_VER(dev_priv) < 9)  in intel_enable_ddi_dp()
2814 		[PORT_A] = TRANSCODER_EDP,  in gen9_chicken_trans_reg_by_port()
2823 	if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))  in gen9_chicken_trans_reg_by_port()
2824 		port = PORT_A;  in gen9_chicken_trans_reg_by_port()
3194 	if (port == PORT_A && DISPLAY_VER(dev_priv) < 12)  in intel_ddi_set_idle_link_train()
3636 	if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)  in intel_ddi_compute_config()
4061 	if (dig_port->base.port != PORT_A)  in intel_ddi_a_force_4_lanes()
4086 	if (port == PORT_A || port == PORT_E) {  in intel_ddi_max_lanes()
4087 		if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)  in intel_ddi_max_lanes()
4088 			max_lanes = port == PORT_A ? 4 : 0;  in intel_ddi_max_lanes()
4123 		return HPD_PORT_A + port - PORT_A;  in xelpd_hpd_pin()
4132 		return HPD_PORT_A + port - PORT_A;  in dg1_hpd_pin()
4141 		return HPD_PORT_A + port - PORT_A;  in tgl_hpd_pin()
4153 		return HPD_PORT_A + port - PORT_A;  in rkl_hpd_pin()
4162 		return HPD_PORT_A + port - PORT_A;  in icl_hpd_pin()
4174 	return HPD_PORT_A + port - PORT_A;  in ehl_hpd_pin()
4182 	return HPD_PORT_A + port - PORT_A;  in skl_hpd_pin()
4500 		if (port == PORT_A || IS_GEMINILAKE(dev_priv) ||  in intel_ddi_init()
4506 		if (port == PORT_A)  in intel_ddi_init()