Lines Matching full:vbl
518 * Wait for psr to idle out after enabling the VBL interrupts in intel_pipe_update_start()
519 * VBL interrupts will start the PSR exit and prevent a PSR in intel_pipe_update_start()
596 if (h >= ARRAY_SIZE(crtc->debug.vbl.times)) in dbg_vblank_evade()
597 h = ARRAY_SIZE(crtc->debug.vbl.times) - 1; in dbg_vblank_evade()
598 crtc->debug.vbl.times[h]++; in dbg_vblank_evade()
600 crtc->debug.vbl.sum += delta; in dbg_vblank_evade()
601 if (!crtc->debug.vbl.min || delta < crtc->debug.vbl.min) in dbg_vblank_evade()
602 crtc->debug.vbl.min = delta; in dbg_vblank_evade()
603 if (delta > crtc->debug.vbl.max) in dbg_vblank_evade()
604 crtc->debug.vbl.max = delta; in dbg_vblank_evade()
612 crtc->debug.vbl.over++; in dbg_vblank_evade()