Lines Matching refs:adpa

169 	u32 adpa;  in intel_crt_set_dpms()  local
172 adpa = ADPA_HOTPLUG_BITS; in intel_crt_set_dpms()
174 adpa = 0; in intel_crt_set_dpms()
177 adpa |= ADPA_HSYNC_ACTIVE_HIGH; in intel_crt_set_dpms()
179 adpa |= ADPA_VSYNC_ACTIVE_HIGH; in intel_crt_set_dpms()
185 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe); in intel_crt_set_dpms()
187 adpa |= ADPA_PIPE_SEL(crtc->pipe); in intel_crt_set_dpms()
194 adpa |= ADPA_DAC_ENABLE; in intel_crt_set_dpms()
197 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; in intel_crt_set_dpms()
200 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; in intel_crt_set_dpms()
203 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; in intel_crt_set_dpms()
207 intel_de_write(dev_priv, crt->adpa_reg, adpa); in intel_crt_set_dpms()
458 u32 adpa; in ilk_crt_detect_hotplug() local
468 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
470 "trigger hotplug detect cycle: adpa=0x%x\n", adpa); in ilk_crt_detect_hotplug()
472 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; in ilk_crt_detect_hotplug()
474 adpa &= ~ADPA_DAC_ENABLE; in ilk_crt_detect_hotplug()
476 intel_de_write(dev_priv, crt->adpa_reg, adpa); in ilk_crt_detect_hotplug()
492 adpa = intel_de_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
493 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) in ilk_crt_detect_hotplug()
498 adpa, ret); in ilk_crt_detect_hotplug()
509 u32 adpa; in valleyview_crt_detect_hotplug() local
527 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); in valleyview_crt_detect_hotplug()
529 "trigger hotplug detect cycle: adpa=0x%x\n", adpa); in valleyview_crt_detect_hotplug()
531 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; in valleyview_crt_detect_hotplug()
533 intel_de_write(dev_priv, crt->adpa_reg, adpa); in valleyview_crt_detect_hotplug()
543 adpa = intel_de_read(dev_priv, crt->adpa_reg); in valleyview_crt_detect_hotplug()
544 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) in valleyview_crt_detect_hotplug()
550 "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); in valleyview_crt_detect_hotplug()
956 u32 adpa; in intel_crt_reset() local
958 adpa = intel_de_read(dev_priv, crt->adpa_reg); in intel_crt_reset()
959 adpa &= ~ADPA_CRT_HOTPLUG_MASK; in intel_crt_reset()
960 adpa |= ADPA_HOTPLUG_BITS; in intel_crt_reset()
961 intel_de_write(dev_priv, crt->adpa_reg, adpa); in intel_crt_reset()
964 drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa); in intel_crt_reset()
1000 u32 adpa; in intel_crt_init() local
1009 adpa = intel_de_read(dev_priv, adpa_reg); in intel_crt_init()
1010 if ((adpa & ADPA_DAC_ENABLE) == 0) { in intel_crt_init()
1020 adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); in intel_crt_init()
1023 intel_de_write(dev_priv, adpa_reg, adpa); in intel_crt_init()