54 icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)  in icl_get_procmon_ref_values()  argument
59 	val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy));  in icl_get_procmon_ref_values()
85 				       enum phy phy)  in icl_set_procmon_ref_values()  argument
90 	procmon = icl_get_procmon_ref_values(dev_priv, phy);  in icl_set_procmon_ref_values()
92 	val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy));  in icl_set_procmon_ref_values()
95 	intel_de_write(dev_priv, ICL_PORT_COMP_DW1(phy), val);  in icl_set_procmon_ref_values()
97 	intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9);  in icl_set_procmon_ref_values()
98 	intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10);  in icl_set_procmon_ref_values()
102 			  enum phy phy, i915_reg_t reg, u32 mask,  in check_phy_reg()  argument
111 			phy_name(phy),  in check_phy_reg()
120 					  enum phy phy)  in icl_verify_procmon_ref_values()  argument
125 	procmon = icl_get_procmon_ref_values(dev_priv, phy);  in icl_verify_procmon_ref_values()
129 		    phy_name(phy), procmon->name);  in icl_verify_procmon_ref_values()
131 	ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),  in icl_verify_procmon_ref_values()
133 	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy),  in icl_verify_procmon_ref_values()
135 	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy),  in icl_verify_procmon_ref_values()
141 static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)  in has_phy_misc()  argument
153 		return phy == PHY_A;  in has_phy_misc()
157 		return phy < PHY_C;  in has_phy_misc()
163 				  enum phy phy)  in icl_combo_phy_enabled()  argument
166 	if (!has_phy_misc(dev_priv, phy))  in icl_combo_phy_enabled()
167 		return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT;  in icl_combo_phy_enabled()
169 		return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) &  in icl_combo_phy_enabled()
171 			(intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT);  in icl_combo_phy_enabled()
201 static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)  in phy_is_master()  argument
219 	if (phy == PHY_A)  in phy_is_master()
222 		return phy == PHY_D;  in phy_is_master()
224 		return phy == PHY_C;  in phy_is_master()
230 				       enum phy phy)  in icl_combo_phy_verify_state()  argument
235 	if (!icl_combo_phy_enabled(dev_priv, phy))  in icl_combo_phy_verify_state()
239 		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN(0, phy),  in icl_combo_phy_verify_state()
245 		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy),  in icl_combo_phy_verify_state()
250 	ret &= icl_verify_procmon_ref_values(dev_priv, phy);  in icl_combo_phy_verify_state()
252 	if (phy_is_master(dev_priv, phy)) {  in icl_combo_phy_verify_state()
253 		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),  in icl_combo_phy_verify_state()
260 			ret &= check_phy_reg(dev_priv, phy, ICL_PHY_MISC(phy),  in icl_combo_phy_verify_state()
266 	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy),  in icl_combo_phy_verify_state()
273 				    enum phy phy, bool is_dsi,  in intel_combo_phy_power_up_lanes()  argument
318 	val = intel_de_read(dev_priv, ICL_PORT_CL_DW10(phy));  in intel_combo_phy_power_up_lanes()
321 	intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val);  in intel_combo_phy_power_up_lanes()
326 	enum phy phy;  in icl_combo_phys_init()  local
328 	for_each_combo_phy(dev_priv, phy) {  in icl_combo_phys_init()
331 		if (icl_combo_phy_verify_state(dev_priv, phy)) {  in icl_combo_phys_init()
334 				phy_name(phy));  in icl_combo_phys_init()
338 		if (!has_phy_misc(dev_priv, phy))  in icl_combo_phys_init()
349 		val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));  in icl_combo_phys_init()
350 		if (IS_JSL_EHL(dev_priv) && phy == PHY_A) {  in icl_combo_phys_init()
358 		intel_de_write(dev_priv, ICL_PHY_MISC(phy), val);  in icl_combo_phys_init()
362 			val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN(0, phy));  in icl_combo_phys_init()
366 			intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);  in icl_combo_phys_init()
368 			val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));  in icl_combo_phys_init()
371 			intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);  in icl_combo_phys_init()
374 		icl_set_procmon_ref_values(dev_priv, phy);  in icl_combo_phys_init()
376 		if (phy_is_master(dev_priv, phy)) {  in icl_combo_phys_init()
377 			val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy));  in icl_combo_phys_init()
379 			intel_de_write(dev_priv, ICL_PORT_COMP_DW8(phy), val);  in icl_combo_phys_init()
382 		val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy));  in icl_combo_phys_init()
384 		intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val);  in icl_combo_phys_init()
386 		val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));  in icl_combo_phys_init()
388 		intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);  in icl_combo_phys_init()
394 	enum phy phy;  in icl_combo_phys_uninit()  local
396 	for_each_combo_phy_reverse(dev_priv, phy) {  in icl_combo_phys_uninit()
399 		if (phy == PHY_A &&  in icl_combo_phys_uninit()
400 		    !icl_combo_phy_verify_state(dev_priv, phy)) {  in icl_combo_phys_uninit()
409 					    phy_name(phy));  in icl_combo_phys_uninit()
413 					 phy_name(phy));  in icl_combo_phys_uninit()
417 		if (!has_phy_misc(dev_priv, phy))  in icl_combo_phys_uninit()
420 		val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));  in icl_combo_phys_uninit()
422 		intel_de_write(dev_priv, ICL_PHY_MISC(phy), val);  in icl_combo_phys_uninit()
425 		val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy));  in icl_combo_phys_uninit()
427 		intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val);  in icl_combo_phys_uninit()