Lines Matching +full:bus +full:- +full:dmc
2 * Copyright © 2006-2017 Intel Corporation
59 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
60 * DMC will not change the active CDCLK frequency however, so that part
82 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
89 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
95 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); in intel_cdclk_modeset_calc_cdclk()
101 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
107 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
113 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
119 cdclk_config->cdclk = 266667; in fixed_266mhz_get_cdclk()
125 cdclk_config->cdclk = 333333; in fixed_333mhz_get_cdclk()
131 cdclk_config->cdclk = 400000; in fixed_400mhz_get_cdclk()
137 cdclk_config->cdclk = 450000; in fixed_450mhz_get_cdclk()
143 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i85x_get_cdclk()
151 if (pdev->revision == 0x1) { in i85x_get_cdclk()
152 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
156 pci_bus_read_config_word(pdev->bus, in i85x_get_cdclk()
166 cdclk_config->cdclk = 200000; in i85x_get_cdclk()
169 cdclk_config->cdclk = 250000; in i85x_get_cdclk()
172 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
177 cdclk_config->cdclk = 266667; in i85x_get_cdclk()
185 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i915gm_get_cdclk()
191 cdclk_config->cdclk = 133333; in i915gm_get_cdclk()
197 cdclk_config->cdclk = 333333; in i915gm_get_cdclk()
201 cdclk_config->cdclk = 190000; in i915gm_get_cdclk()
209 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i945gm_get_cdclk()
215 cdclk_config->cdclk = 133333; in i945gm_get_cdclk()
221 cdclk_config->cdclk = 320000; in i945gm_get_cdclk()
225 cdclk_config->cdclk = 200000; in i945gm_get_cdclk()
292 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", in intel_hpll_vco()
295 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); in intel_hpll_vco()
303 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in g33_get_cdclk()
312 cdclk_config->vco = intel_hpll_vco(dev_priv); in g33_get_cdclk()
321 switch (cdclk_config->vco) { in g33_get_cdclk()
338 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in g33_get_cdclk()
343 drm_err(&dev_priv->drm, in g33_get_cdclk()
345 cdclk_config->vco, tmp); in g33_get_cdclk()
346 cdclk_config->cdclk = 190476; in g33_get_cdclk()
352 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in pnv_get_cdclk()
359 cdclk_config->cdclk = 266667; in pnv_get_cdclk()
362 cdclk_config->cdclk = 333333; in pnv_get_cdclk()
365 cdclk_config->cdclk = 444444; in pnv_get_cdclk()
368 cdclk_config->cdclk = 200000; in pnv_get_cdclk()
371 drm_err(&dev_priv->drm, in pnv_get_cdclk()
375 cdclk_config->cdclk = 133333; in pnv_get_cdclk()
378 cdclk_config->cdclk = 166667; in pnv_get_cdclk()
386 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i965gm_get_cdclk()
394 cdclk_config->vco = intel_hpll_vco(dev_priv); in i965gm_get_cdclk()
398 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; in i965gm_get_cdclk()
403 switch (cdclk_config->vco) { in i965gm_get_cdclk()
417 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in i965gm_get_cdclk()
422 drm_err(&dev_priv->drm, in i965gm_get_cdclk()
424 cdclk_config->vco, tmp); in i965gm_get_cdclk()
425 cdclk_config->cdclk = 200000; in i965gm_get_cdclk()
431 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in gm45_get_cdclk()
435 cdclk_config->vco = intel_hpll_vco(dev_priv); in gm45_get_cdclk()
441 switch (cdclk_config->vco) { in gm45_get_cdclk()
445 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; in gm45_get_cdclk()
448 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; in gm45_get_cdclk()
451 drm_err(&dev_priv->drm, in gm45_get_cdclk()
453 cdclk_config->vco, tmp); in gm45_get_cdclk()
454 cdclk_config->cdclk = 222222; in gm45_get_cdclk()
466 cdclk_config->cdclk = 800000; in hsw_get_cdclk()
468 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
470 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
472 cdclk_config->cdclk = 337500; in hsw_get_cdclk()
474 cdclk_config->cdclk = 540000; in hsw_get_cdclk()
479 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? in vlv_calc_cdclk()
512 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; in vlv_calc_voltage_level()
524 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); in vlv_get_cdclk()
525 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", in vlv_get_cdclk()
527 cdclk_config->vco); in vlv_get_cdclk()
535 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> in vlv_get_cdclk()
538 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> in vlv_get_cdclk()
551 if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
562 * WA - write default credits before re-programming in vlv_program_pfi_credits()
575 drm_WARN_ON(&dev_priv->drm, in vlv_program_pfi_credits()
583 int cdclk = cdclk_config->cdclk; in vlv_set_cdclk()
584 u32 val, cmd = cdclk_config->voltage_level; in vlv_set_cdclk()
619 drm_err(&dev_priv->drm, in vlv_set_cdclk()
626 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, in vlv_set_cdclk()
627 cdclk) - 1; in vlv_set_cdclk()
638 drm_err(&dev_priv->drm, in vlv_set_cdclk()
642 /* adjust self-refresh exit latency value */ in vlv_set_cdclk()
672 int cdclk = cdclk_config->cdclk; in chv_set_cdclk()
673 u32 val, cmd = cdclk_config->voltage_level; in chv_set_cdclk()
703 drm_err(&dev_priv->drm, in chv_set_cdclk()
750 cdclk_config->cdclk = 800000; in bdw_get_cdclk()
752 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
754 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
756 cdclk_config->cdclk = 540000; in bdw_get_cdclk()
758 cdclk_config->cdclk = 337500; in bdw_get_cdclk()
760 cdclk_config->cdclk = 675000; in bdw_get_cdclk()
766 cdclk_config->voltage_level = in bdw_get_cdclk()
767 bdw_calc_voltage_level(cdclk_config->cdclk); in bdw_get_cdclk()
791 int cdclk = cdclk_config->cdclk; in bdw_set_cdclk()
794 if (drm_WARN(&dev_priv->drm, in bdw_set_cdclk()
803 ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); in bdw_set_cdclk()
805 drm_err(&dev_priv->drm, in bdw_set_cdclk()
819 drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); in bdw_set_cdclk()
829 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n"); in bdw_set_cdclk()
831 snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ, in bdw_set_cdclk()
832 cdclk_config->voltage_level); in bdw_set_cdclk()
835 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); in bdw_set_cdclk()
880 cdclk_config->ref = 24000; in skl_dpll0_update()
881 cdclk_config->vco = 0; in skl_dpll0_update()
887 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0)) in skl_dpll0_update()
892 if (drm_WARN_ON(&dev_priv->drm, in skl_dpll0_update()
904 cdclk_config->vco = 8100000; in skl_dpll0_update()
908 cdclk_config->vco = 8640000; in skl_dpll0_update()
923 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; in skl_get_cdclk()
925 if (cdclk_config->vco == 0) in skl_get_cdclk()
930 if (cdclk_config->vco == 8640000) { in skl_get_cdclk()
933 cdclk_config->cdclk = 432000; in skl_get_cdclk()
936 cdclk_config->cdclk = 308571; in skl_get_cdclk()
939 cdclk_config->cdclk = 540000; in skl_get_cdclk()
942 cdclk_config->cdclk = 617143; in skl_get_cdclk()
951 cdclk_config->cdclk = 450000; in skl_get_cdclk()
954 cdclk_config->cdclk = 337500; in skl_get_cdclk()
957 cdclk_config->cdclk = 540000; in skl_get_cdclk()
960 cdclk_config->cdclk = 675000; in skl_get_cdclk()
973 cdclk_config->voltage_level = in skl_get_cdclk()
974 skl_calc_voltage_level(cdclk_config->cdclk); in skl_get_cdclk()
977 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
980 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); in skl_cdclk_decimal()
986 bool changed = dev_priv->skl_preferred_vco_freq != vco; in skl_set_preferred_cdclk_vco()
988 dev_priv->skl_preferred_vco_freq = vco; in skl_set_preferred_cdclk_vco()
996 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); in skl_dpll0_link_rate()
1027 drm_err(&dev_priv->drm, "DPLL0 not locked\n"); in skl_dpll0_enable()
1029 dev_priv->display.cdclk.hw.vco = vco; in skl_dpll0_enable()
1041 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); in skl_dpll0_disable()
1043 dev_priv->display.cdclk.hw.vco = 0; in skl_dpll0_disable()
1051 drm_WARN_ON(&dev_priv->drm, in skl_cdclk_freq_sel()
1052 cdclk != dev_priv->display.cdclk.hw.bypass); in skl_cdclk_freq_sel()
1053 drm_WARN_ON(&dev_priv->drm, vco != 0); in skl_cdclk_freq_sel()
1073 int cdclk = cdclk_config->cdclk; in skl_set_cdclk()
1074 int vco = cdclk_config->vco; in skl_set_cdclk()
1086 drm_WARN_ON_ONCE(&dev_priv->drm, in skl_set_cdclk()
1089 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1094 drm_err(&dev_priv->drm, in skl_set_cdclk()
1101 if (dev_priv->display.cdclk.hw.vco != 0 && in skl_set_cdclk()
1102 dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1107 if (dev_priv->display.cdclk.hw.vco != vco) { in skl_set_cdclk()
1119 if (dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1135 snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1136 cdclk_config->voltage_level); in skl_set_cdclk()
1146 * check if the pre-os initialized the display in skl_sanitize_cdclk()
1148 * pre-os which can be used by the OS drivers to check the status in skl_sanitize_cdclk()
1154 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in skl_sanitize_cdclk()
1157 if (dev_priv->display.cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1158 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in skl_sanitize_cdclk()
1164 * decimal part is programmed wrong from BIOS where pre-os does not in skl_sanitize_cdclk()
1169 skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk); in skl_sanitize_cdclk()
1175 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in skl_sanitize_cdclk()
1178 dev_priv->display.cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1180 dev_priv->display.cdclk.hw.vco = -1; in skl_sanitize_cdclk()
1189 if (dev_priv->display.cdclk.hw.cdclk != 0 && in skl_cdclk_init_hw()
1190 dev_priv->display.cdclk.hw.vco != 0) { in skl_cdclk_init_hw()
1195 if (dev_priv->skl_preferred_vco_freq == 0) in skl_cdclk_init_hw()
1197 dev_priv->display.cdclk.hw.vco); in skl_cdclk_init_hw()
1201 cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_init_hw()
1203 cdclk_config.vco = dev_priv->skl_preferred_vco_freq; in skl_cdclk_init_hw()
1214 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_uninit_hw()
1355 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk()
1359 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk()
1363 drm_WARN(&dev_priv->drm, 1, in bxt_calc_cdclk()
1365 min_cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk()
1371 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk_pll_vco()
1374 if (cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_calc_cdclk_pll_vco()
1378 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk_pll_vco()
1380 return dev_priv->display.cdclk.hw.ref * table[i].ratio; in bxt_calc_cdclk_pll_vco()
1382 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", in bxt_calc_cdclk_pll_vco()
1383 cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk_pll_vco()
1436 cdclk_config->ref = 24000; in icl_readout_refclk()
1439 cdclk_config->ref = 19200; in icl_readout_refclk()
1442 cdclk_config->ref = 38400; in icl_readout_refclk()
1453 cdclk_config->ref = 38400; in bxt_de_pll_readout()
1457 cdclk_config->ref = 19200; in bxt_de_pll_readout()
1466 cdclk_config->vco = 0; in bxt_de_pll_readout()
1479 cdclk_config->vco = ratio * cdclk_config->ref; in bxt_de_pll_readout()
1492 cdclk_config->bypass = cdclk_config->ref / 2; in bxt_get_cdclk()
1494 cdclk_config->bypass = 50000; in bxt_get_cdclk()
1496 cdclk_config->bypass = cdclk_config->ref; in bxt_get_cdclk()
1498 if (cdclk_config->vco == 0) { in bxt_get_cdclk()
1499 cdclk_config->cdclk = cdclk_config->bypass; in bxt_get_cdclk()
1531 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size); in bxt_get_cdclk()
1533 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * in bxt_get_cdclk()
1534 cdclk_config->vco, size * div); in bxt_get_cdclk()
1536 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); in bxt_get_cdclk()
1544 cdclk_config->voltage_level = in bxt_get_cdclk()
1545 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk); in bxt_get_cdclk()
1555 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n"); in bxt_de_pll_disable()
1557 dev_priv->display.cdclk.hw.vco = 0; in bxt_de_pll_disable()
1562 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in bxt_de_pll_enable()
1572 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n"); in bxt_de_pll_enable()
1574 dev_priv->display.cdclk.hw.vco = vco; in bxt_de_pll_enable()
1584 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n"); in icl_cdclk_pll_disable()
1586 dev_priv->display.cdclk.hw.vco = 0; in icl_cdclk_pll_disable()
1591 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in icl_cdclk_pll_enable()
1602 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n"); in icl_cdclk_pll_enable()
1604 dev_priv->display.cdclk.hw.vco = vco; in icl_cdclk_pll_enable()
1609 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in adlp_cdclk_pll_crawl()
1623 drm_err(&dev_priv->drm, "timeout waiting for FREQ change request ack\n"); in adlp_cdclk_pll_crawl()
1628 dev_priv->display.cdclk.hw.vco = vco; in adlp_cdclk_pll_crawl()
1657 drm_WARN_ON(&dev_priv->drm, in bxt_cdclk_cd2x_div_sel()
1658 cdclk != dev_priv->display.cdclk.hw.bypass); in bxt_cdclk_cd2x_div_sel()
1659 drm_WARN_ON(&dev_priv->drm, vco != 0); in bxt_cdclk_cd2x_div_sel()
1675 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in cdclk_squash_waveform()
1678 if (cdclk == dev_priv->display.cdclk.hw.bypass) in cdclk_squash_waveform()
1682 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in cdclk_squash_waveform()
1686 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", in cdclk_squash_waveform()
1687 cdclk, dev_priv->display.cdclk.hw.ref); in cdclk_squash_waveform()
1696 int cdclk = cdclk_config->cdclk; in bxt_set_cdclk()
1697 int vco = cdclk_config->vco; in bxt_set_cdclk()
1705 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in bxt_set_cdclk()
1714 ret = snb_pcode_write_timeout(&dev_priv->uncore, in bxt_set_cdclk()
1718 drm_err(&dev_priv->drm, in bxt_set_cdclk()
1724 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0) { in bxt_set_cdclk()
1725 if (dev_priv->display.cdclk.hw.vco != vco) in bxt_set_cdclk()
1728 if (dev_priv->display.cdclk.hw.vco != 0 && in bxt_set_cdclk()
1729 dev_priv->display.cdclk.hw.vco != vco) in bxt_set_cdclk()
1732 if (dev_priv->display.cdclk.hw.vco != vco) in bxt_set_cdclk()
1735 if (dev_priv->display.cdclk.hw.vco != 0 && in bxt_set_cdclk()
1736 dev_priv->display.cdclk.hw.vco != vco) in bxt_set_cdclk()
1739 if (dev_priv->display.cdclk.hw.vco != vco) in bxt_set_cdclk()
1777 ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in bxt_set_cdclk()
1778 cdclk_config->voltage_level); in bxt_set_cdclk()
1786 ret = snb_pcode_write_timeout(&dev_priv->uncore, in bxt_set_cdclk()
1788 cdclk_config->voltage_level, in bxt_set_cdclk()
1793 drm_err(&dev_priv->drm, in bxt_set_cdclk()
1806 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
1815 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in bxt_sanitize_cdclk()
1817 if (dev_priv->display.cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
1818 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_sanitize_cdclk()
1836 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); in bxt_sanitize_cdclk()
1837 if (cdclk != dev_priv->display.cdclk.hw.cdclk) in bxt_sanitize_cdclk()
1842 if (vco != dev_priv->display.cdclk.hw.vco) in bxt_sanitize_cdclk()
1849 clock = dev_priv->display.cdclk.hw.vco / 2; in bxt_sanitize_cdclk()
1851 clock = dev_priv->display.cdclk.hw.cdclk; in bxt_sanitize_cdclk()
1854 dev_priv->display.cdclk.hw.vco); in bxt_sanitize_cdclk()
1861 dev_priv->display.cdclk.hw.cdclk >= 500000) in bxt_sanitize_cdclk()
1869 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in bxt_sanitize_cdclk()
1872 dev_priv->display.cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
1875 dev_priv->display.cdclk.hw.vco = -1; in bxt_sanitize_cdclk()
1884 if (dev_priv->display.cdclk.hw.cdclk != 0 && in bxt_cdclk_init_hw()
1885 dev_priv->display.cdclk.hw.vco != 0) in bxt_cdclk_init_hw()
1888 cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_init_hw()
1892 * - The initial CDCLK needs to be read from VBT. in bxt_cdclk_init_hw()
1905 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_uninit_hw()
1916 * intel_cdclk_init_hw - Initialize CDCLK hardware
1919 * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and
1921 * during the display core initialization sequence, after which the DMC will
1933 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
1960 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); in intel_cdclk_can_crawl()
1961 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); in intel_cdclk_can_crawl()
1963 return a->vco != 0 && b->vco != 0 && in intel_cdclk_can_crawl()
1964 a->vco != b->vco && in intel_cdclk_can_crawl()
1966 a->ref == b->ref; in intel_cdclk_can_crawl()
1982 return a->cdclk != b->cdclk && in intel_cdclk_can_squash()
1983 a->vco != 0 && in intel_cdclk_can_squash()
1984 a->vco == b->vco && in intel_cdclk_can_squash()
1985 a->ref == b->ref; in intel_cdclk_can_squash()
1989 * intel_cdclk_needs_modeset - Determine if changong between the CDCLK
2001 return a->cdclk != b->cdclk || in intel_cdclk_needs_modeset()
2002 a->vco != b->vco || in intel_cdclk_needs_modeset()
2003 a->ref != b->ref; in intel_cdclk_needs_modeset()
2007 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
2034 return a->cdclk != b->cdclk && in intel_cdclk_can_cd2x_update()
2035 a->vco != 0 && in intel_cdclk_can_cd2x_update()
2036 a->vco == b->vco && in intel_cdclk_can_cd2x_update()
2037 a->ref == b->ref; in intel_cdclk_can_cd2x_update()
2041 * intel_cdclk_changed - Determine if two CDCLK configurations are different
2052 a->voltage_level != b->voltage_level; in intel_cdclk_changed()
2059 drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", in intel_cdclk_dump_config()
2060 context, cdclk_config->cdclk, cdclk_config->vco, in intel_cdclk_dump_config()
2061 cdclk_config->ref, cdclk_config->bypass, in intel_cdclk_dump_config()
2062 cdclk_config->voltage_level); in intel_cdclk_dump_config()
2066 * intel_set_cdclk - Push the CDCLK configuration to the hardware
2080 if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config)) in intel_set_cdclk()
2083 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk)) in intel_set_cdclk()
2088 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in intel_set_cdclk()
2101 mutex_lock(&dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2102 for_each_intel_dp(&dev_priv->drm, encoder) { in intel_set_cdclk()
2105 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, in intel_set_cdclk()
2106 &dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2111 for_each_intel_dp(&dev_priv->drm, encoder) { in intel_set_cdclk()
2114 mutex_unlock(&intel_dp->aux.hw_mutex); in intel_set_cdclk()
2116 mutex_unlock(&dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2118 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in intel_set_cdclk()
2126 if (drm_WARN(&dev_priv->drm, in intel_set_cdclk()
2127 intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config), in intel_set_cdclk()
2129 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]"); in intel_set_cdclk()
2135 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
2144 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_set_cdclk_pre_plane_update()
2149 enum pipe pipe = new_cdclk_state->pipe; in intel_set_cdclk_pre_plane_update()
2151 if (!intel_cdclk_changed(&old_cdclk_state->actual, in intel_set_cdclk_pre_plane_update()
2152 &new_cdclk_state->actual)) in intel_set_cdclk_pre_plane_update()
2156 old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) { in intel_set_cdclk_pre_plane_update()
2157 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_pre_plane_update()
2159 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); in intel_set_cdclk_pre_plane_update()
2164 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2173 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_set_cdclk_post_plane_update()
2178 enum pipe pipe = new_cdclk_state->pipe; in intel_set_cdclk_post_plane_update()
2180 if (!intel_cdclk_changed(&old_cdclk_state->actual, in intel_set_cdclk_post_plane_update()
2181 &new_cdclk_state->actual)) in intel_set_cdclk_post_plane_update()
2185 old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) { in intel_set_cdclk_post_plane_update()
2186 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_post_plane_update()
2188 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); in intel_set_cdclk_post_plane_update()
2194 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_pixel_rate_to_cdclk()
2195 int pixel_rate = crtc_state->pixel_rate; in intel_pixel_rate_to_cdclk()
2204 else if (crtc_state->double_wide) in intel_pixel_rate_to_cdclk()
2212 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_planes_min_cdclk()
2213 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_planes_min_cdclk()
2217 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) in intel_planes_min_cdclk()
2218 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk); in intel_planes_min_cdclk()
2226 to_i915(crtc_state->uapi.crtc->dev); in intel_crtc_compute_min_cdclk()
2229 if (!crtc_state->hw.enable) in intel_crtc_compute_min_cdclk()
2244 crtc_state->has_audio && in intel_crtc_compute_min_cdclk()
2245 crtc_state->port_clock >= 540000 && in intel_crtc_compute_min_cdclk()
2246 crtc_state->lane_count == 4) { in intel_crtc_compute_min_cdclk()
2260 if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9) in intel_crtc_compute_min_cdclk()
2271 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) in intel_crtc_compute_min_cdclk()
2272 min_cdclk = max(crtc_state->port_clock, min_cdclk); in intel_crtc_compute_min_cdclk()
2299 if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split) in intel_crtc_compute_min_cdclk()
2300 min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); in intel_crtc_compute_min_cdclk()
2317 min_t(int, crtc_state->pixel_rate, in intel_crtc_compute_min_cdclk()
2318 dev_priv->display.cdclk.max_cdclk_freq)); in intel_crtc_compute_min_cdclk()
2326 struct intel_atomic_state *state = cdclk_state->base.state; in intel_compute_min_cdclk()
2327 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_compute_min_cdclk()
2341 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk) in intel_compute_min_cdclk()
2344 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; in intel_compute_min_cdclk()
2346 ret = intel_atomic_lock_global_state(&cdclk_state->base); in intel_compute_min_cdclk()
2355 if (cdclk_state->bw_min_cdclk != min_cdclk) { in intel_compute_min_cdclk()
2358 cdclk_state->bw_min_cdclk = min_cdclk; in intel_compute_min_cdclk()
2360 ret = intel_atomic_lock_global_state(&cdclk_state->base); in intel_compute_min_cdclk()
2366 min_cdclk = max(cdclk_state->force_min_cdclk, in intel_compute_min_cdclk()
2367 cdclk_state->bw_min_cdclk); in intel_compute_min_cdclk()
2369 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); in intel_compute_min_cdclk()
2371 if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) { in intel_compute_min_cdclk()
2372 drm_dbg_kms(&dev_priv->drm, in intel_compute_min_cdclk()
2374 min_cdclk, dev_priv->display.cdclk.max_cdclk_freq); in intel_compute_min_cdclk()
2375 return -EINVAL; in intel_compute_min_cdclk()
2396 struct intel_atomic_state *state = cdclk_state->base.state; in bxt_compute_min_voltage_level()
2397 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in bxt_compute_min_voltage_level()
2407 if (crtc_state->hw.enable) in bxt_compute_min_voltage_level()
2408 min_voltage_level = crtc_state->min_voltage_level; in bxt_compute_min_voltage_level()
2412 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) in bxt_compute_min_voltage_level()
2415 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; in bxt_compute_min_voltage_level()
2417 ret = intel_atomic_lock_global_state(&cdclk_state->base); in bxt_compute_min_voltage_level()
2424 min_voltage_level = max(cdclk_state->min_voltage_level[pipe], in bxt_compute_min_voltage_level()
2432 struct intel_atomic_state *state = cdclk_state->base.state; in vlv_modeset_calc_cdclk()
2433 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in vlv_modeset_calc_cdclk()
2442 cdclk_state->logical.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2443 cdclk_state->logical.voltage_level = in vlv_modeset_calc_cdclk()
2446 if (!cdclk_state->active_pipes) { in vlv_modeset_calc_cdclk()
2447 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in vlv_modeset_calc_cdclk()
2449 cdclk_state->actual.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2450 cdclk_state->actual.voltage_level = in vlv_modeset_calc_cdclk()
2453 cdclk_state->actual = cdclk_state->logical; in vlv_modeset_calc_cdclk()
2473 cdclk_state->logical.cdclk = cdclk; in bdw_modeset_calc_cdclk()
2474 cdclk_state->logical.voltage_level = in bdw_modeset_calc_cdclk()
2477 if (!cdclk_state->active_pipes) { in bdw_modeset_calc_cdclk()
2478 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); in bdw_modeset_calc_cdclk()
2480 cdclk_state->actual.cdclk = cdclk; in bdw_modeset_calc_cdclk()
2481 cdclk_state->actual.voltage_level = in bdw_modeset_calc_cdclk()
2484 cdclk_state->actual = cdclk_state->logical; in bdw_modeset_calc_cdclk()
2492 struct intel_atomic_state *state = cdclk_state->base.state; in skl_dpll0_vco()
2493 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in skl_dpll0_vco()
2498 vco = cdclk_state->logical.vco; in skl_dpll0_vco()
2500 vco = dev_priv->skl_preferred_vco_freq; in skl_dpll0_vco()
2503 if (!crtc_state->hw.enable) in skl_dpll0_vco()
2513 switch (crtc_state->port_clock / 2) { in skl_dpll0_vco()
2543 cdclk_state->logical.vco = vco; in skl_modeset_calc_cdclk()
2544 cdclk_state->logical.cdclk = cdclk; in skl_modeset_calc_cdclk()
2545 cdclk_state->logical.voltage_level = in skl_modeset_calc_cdclk()
2548 if (!cdclk_state->active_pipes) { in skl_modeset_calc_cdclk()
2549 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); in skl_modeset_calc_cdclk()
2551 cdclk_state->actual.vco = vco; in skl_modeset_calc_cdclk()
2552 cdclk_state->actual.cdclk = cdclk; in skl_modeset_calc_cdclk()
2553 cdclk_state->actual.voltage_level = in skl_modeset_calc_cdclk()
2556 cdclk_state->actual = cdclk_state->logical; in skl_modeset_calc_cdclk()
2564 struct intel_atomic_state *state = cdclk_state->base.state; in bxt_modeset_calc_cdclk()
2565 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in bxt_modeset_calc_cdclk()
2579 cdclk_state->logical.vco = vco; in bxt_modeset_calc_cdclk()
2580 cdclk_state->logical.cdclk = cdclk; in bxt_modeset_calc_cdclk()
2581 cdclk_state->logical.voltage_level = in bxt_modeset_calc_cdclk()
2585 if (!cdclk_state->active_pipes) { in bxt_modeset_calc_cdclk()
2586 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in bxt_modeset_calc_cdclk()
2589 cdclk_state->actual.vco = vco; in bxt_modeset_calc_cdclk()
2590 cdclk_state->actual.cdclk = cdclk; in bxt_modeset_calc_cdclk()
2591 cdclk_state->actual.voltage_level = in bxt_modeset_calc_cdclk()
2594 cdclk_state->actual = cdclk_state->logical; in bxt_modeset_calc_cdclk()
2620 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); in intel_cdclk_duplicate_state()
2624 cdclk_state->pipe = INVALID_PIPE; in intel_cdclk_duplicate_state()
2626 return &cdclk_state->base; in intel_cdclk_duplicate_state()
2643 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_atomic_get_cdclk_state()
2646 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj); in intel_atomic_get_cdclk_state()
2682 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) in intel_cdclk_atomic_check()
2694 return -ENOMEM; in intel_cdclk_init()
2696 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, in intel_cdclk_init()
2697 &cdclk_state->base, &intel_cdclk_funcs); in intel_cdclk_init()
2704 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_modeset_calc_cdclk()
2716 new_cdclk_state->active_pipes = in intel_modeset_calc_cdclk()
2717 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); in intel_modeset_calc_cdclk()
2723 if (intel_cdclk_changed(&old_cdclk_state->actual, in intel_modeset_calc_cdclk()
2724 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
2729 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); in intel_modeset_calc_cdclk()
2732 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || in intel_modeset_calc_cdclk()
2733 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk || in intel_modeset_calc_cdclk()
2734 intel_cdclk_changed(&old_cdclk_state->logical, in intel_modeset_calc_cdclk()
2735 &new_cdclk_state->logical)) { in intel_modeset_calc_cdclk()
2736 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); in intel_modeset_calc_cdclk()
2743 if (is_power_of_2(new_cdclk_state->active_pipes) && in intel_modeset_calc_cdclk()
2745 &old_cdclk_state->actual, in intel_modeset_calc_cdclk()
2746 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
2750 pipe = ilog2(new_cdclk_state->active_pipes); in intel_modeset_calc_cdclk()
2753 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); in intel_modeset_calc_cdclk()
2757 if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) in intel_modeset_calc_cdclk()
2762 &old_cdclk_state->actual, in intel_modeset_calc_cdclk()
2763 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
2764 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2767 &old_cdclk_state->actual, in intel_modeset_calc_cdclk()
2768 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
2769 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2772 new_cdclk_state->pipe = pipe; in intel_modeset_calc_cdclk()
2774 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2777 } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual, in intel_modeset_calc_cdclk()
2778 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
2784 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2788 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2790 new_cdclk_state->logical.cdclk, in intel_modeset_calc_cdclk()
2791 new_cdclk_state->actual.cdclk); in intel_modeset_calc_cdclk()
2792 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2794 new_cdclk_state->logical.voltage_level, in intel_modeset_calc_cdclk()
2795 new_cdclk_state->actual.voltage_level); in intel_modeset_calc_cdclk()
2802 int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq; in intel_compute_max_dotclk()
2818 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2828 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
2829 dev_priv->display.cdclk.max_cdclk_freq = 552000; in intel_update_max_cdclk()
2831 dev_priv->display.cdclk.max_cdclk_freq = 556800; in intel_update_max_cdclk()
2833 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
2834 dev_priv->display.cdclk.max_cdclk_freq = 648000; in intel_update_max_cdclk()
2836 dev_priv->display.cdclk.max_cdclk_freq = 652800; in intel_update_max_cdclk()
2838 dev_priv->display.cdclk.max_cdclk_freq = 316800; in intel_update_max_cdclk()
2840 dev_priv->display.cdclk.max_cdclk_freq = 624000; in intel_update_max_cdclk()
2845 vco = dev_priv->skl_preferred_vco_freq; in intel_update_max_cdclk()
2846 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); in intel_update_max_cdclk()
2862 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()
2871 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
2873 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
2875 dev_priv->display.cdclk.max_cdclk_freq = 540000; in intel_update_max_cdclk()
2877 dev_priv->display.cdclk.max_cdclk_freq = 675000; in intel_update_max_cdclk()
2879 dev_priv->display.cdclk.max_cdclk_freq = 320000; in intel_update_max_cdclk()
2881 dev_priv->display.cdclk.max_cdclk_freq = 400000; in intel_update_max_cdclk()
2884 dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk; in intel_update_max_cdclk()
2887 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); in intel_update_max_cdclk()
2889 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n", in intel_update_max_cdclk()
2890 dev_priv->display.cdclk.max_cdclk_freq); in intel_update_max_cdclk()
2892 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n", in intel_update_max_cdclk()
2893 dev_priv->max_dotclk_freq); in intel_update_max_cdclk()
2897 * intel_update_cdclk - Determine the current CDCLK frequency
2904 intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw); in intel_update_cdclk()
2914 DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000)); in intel_update_cdclk()
2949 fraction) - 1); in cnp_rawclk()
3027 * intel_read_rawclk - Determine the current RAWCLK frequency
3191 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
3197 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3198 dev_priv->display.cdclk.table = dg2_cdclk_table; in intel_init_cdclk_hooks()
3200 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3201 /* Wa_22011320316:adl-p[a0] */ in intel_init_cdclk_hooks()
3203 dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; in intel_init_cdclk_hooks()
3205 dev_priv->display.cdclk.table = adlp_cdclk_table; in intel_init_cdclk_hooks()
3207 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3208 dev_priv->display.cdclk.table = rkl_cdclk_table; in intel_init_cdclk_hooks()
3210 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3211 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3213 dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs; in intel_init_cdclk_hooks()
3214 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3216 dev_priv->display.funcs.cdclk = &icl_cdclk_funcs; in intel_init_cdclk_hooks()
3217 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3219 dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs; in intel_init_cdclk_hooks()
3221 dev_priv->display.cdclk.table = glk_cdclk_table; in intel_init_cdclk_hooks()
3223 dev_priv->display.cdclk.table = bxt_cdclk_table; in intel_init_cdclk_hooks()
3225 dev_priv->display.funcs.cdclk = &skl_cdclk_funcs; in intel_init_cdclk_hooks()
3227 dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs; in intel_init_cdclk_hooks()
3229 dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs; in intel_init_cdclk_hooks()
3231 dev_priv->display.funcs.cdclk = &chv_cdclk_funcs; in intel_init_cdclk_hooks()
3233 dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs; in intel_init_cdclk_hooks()
3235 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3237 dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs; in intel_init_cdclk_hooks()
3239 dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs; in intel_init_cdclk_hooks()
3241 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3243 dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs; in intel_init_cdclk_hooks()
3245 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3247 dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs; in intel_init_cdclk_hooks()
3249 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3251 dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs; in intel_init_cdclk_hooks()
3253 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3255 dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs; in intel_init_cdclk_hooks()
3257 dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs; in intel_init_cdclk_hooks()
3259 dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs; in intel_init_cdclk_hooks()
3261 dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs; in intel_init_cdclk_hooks()
3263 dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs; in intel_init_cdclk_hooks()
3265 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()
3268 if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk, in intel_init_cdclk_hooks()
3270 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()