Lines Matching full:display
44 * The display engine uses several different clocks to do its work. There
47 * are the core display clock (CDCLK) and RAWCLK.
49 * CDCLK clocks most of the display pipe logic, and thus its frequency
55 * to minimize power consumption for a given display configuration.
56 * Typically changes to the CDCLK frequency require all the display pipes
82 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
89 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
95 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); in intel_cdclk_modeset_calc_cdclk()
101 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
372 "Unknown pnv display core clock 0x%04x\n", gcfgc); in pnv_get_cdclk()
551 if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
601 * issuing a modeset without actually changing any display after in vlv_set_cdclk()
602 * a system suspend. So grab the display core domain, which covers in vlv_set_cdclk()
648 * so that the core display fetch happens in time to avoid underruns. in vlv_set_cdclk()
689 * issuing a modeset without actually changing any display after in chv_set_cdclk()
690 * a system suspend. So grab the display core domain, which covers in chv_set_cdclk()
1029 dev_priv->display.cdclk.hw.vco = vco; in skl_dpll0_enable()
1043 dev_priv->display.cdclk.hw.vco = 0; in skl_dpll0_disable()
1052 cdclk != dev_priv->display.cdclk.hw.bypass); in skl_cdclk_freq_sel()
1101 if (dev_priv->display.cdclk.hw.vco != 0 && in skl_set_cdclk()
1102 dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1107 if (dev_priv->display.cdclk.hw.vco != vco) { in skl_set_cdclk()
1108 /* Wa Display #1183: skl,kbl,cfl */ in skl_set_cdclk()
1114 /* Wa Display #1183: skl,kbl,cfl */ in skl_set_cdclk()
1119 if (dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1122 /* Wa Display #1183: skl,kbl,cfl */ in skl_set_cdclk()
1129 /* Wa Display #1183: skl,kbl,cfl */ in skl_set_cdclk()
1146 * check if the pre-os initialized the display in skl_sanitize_cdclk()
1154 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in skl_sanitize_cdclk()
1157 if (dev_priv->display.cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1158 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in skl_sanitize_cdclk()
1165 * enable display. Verify the same as well. in skl_sanitize_cdclk()
1169 skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk); in skl_sanitize_cdclk()
1178 dev_priv->display.cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1180 dev_priv->display.cdclk.hw.vco = -1; in skl_sanitize_cdclk()
1189 if (dev_priv->display.cdclk.hw.cdclk != 0 && in skl_cdclk_init_hw()
1190 dev_priv->display.cdclk.hw.vco != 0) { in skl_cdclk_init_hw()
1197 dev_priv->display.cdclk.hw.vco); in skl_cdclk_init_hw()
1201 cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_init_hw()
1214 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_uninit_hw()
1355 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk()
1359 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk()
1365 min_cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk()
1371 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk_pll_vco()
1374 if (cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_calc_cdclk_pll_vco()
1378 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk_pll_vco()
1380 return dev_priv->display.cdclk.hw.ref * table[i].ratio; in bxt_calc_cdclk_pll_vco()
1383 cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk_pll_vco()
1557 dev_priv->display.cdclk.hw.vco = 0; in bxt_de_pll_disable()
1562 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in bxt_de_pll_enable()
1574 dev_priv->display.cdclk.hw.vco = vco; in bxt_de_pll_enable()
1586 dev_priv->display.cdclk.hw.vco = 0; in icl_cdclk_pll_disable()
1591 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in icl_cdclk_pll_enable()
1604 dev_priv->display.cdclk.hw.vco = vco; in icl_cdclk_pll_enable()
1609 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in adlp_cdclk_pll_crawl()
1628 dev_priv->display.cdclk.hw.vco = vco; in adlp_cdclk_pll_crawl()
1658 cdclk != dev_priv->display.cdclk.hw.bypass); in bxt_cdclk_cd2x_div_sel()
1675 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in cdclk_squash_waveform()
1678 if (cdclk == dev_priv->display.cdclk.hw.bypass) in cdclk_squash_waveform()
1682 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in cdclk_squash_waveform()
1687 cdclk, dev_priv->display.cdclk.hw.ref); in cdclk_squash_waveform()
1724 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0) { in bxt_set_cdclk()
1725 if (dev_priv->display.cdclk.hw.vco != vco) in bxt_set_cdclk()
1728 if (dev_priv->display.cdclk.hw.vco != 0 && in bxt_set_cdclk()
1729 dev_priv->display.cdclk.hw.vco != vco) in bxt_set_cdclk()
1732 if (dev_priv->display.cdclk.hw.vco != vco) in bxt_set_cdclk()
1735 if (dev_priv->display.cdclk.hw.vco != 0 && in bxt_set_cdclk()
1736 dev_priv->display.cdclk.hw.vco != vco) in bxt_set_cdclk()
1739 if (dev_priv->display.cdclk.hw.vco != vco) in bxt_set_cdclk()
1806 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
1815 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in bxt_sanitize_cdclk()
1817 if (dev_priv->display.cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
1818 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_sanitize_cdclk()
1836 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); in bxt_sanitize_cdclk()
1837 if (cdclk != dev_priv->display.cdclk.hw.cdclk) in bxt_sanitize_cdclk()
1842 if (vco != dev_priv->display.cdclk.hw.vco) in bxt_sanitize_cdclk()
1849 clock = dev_priv->display.cdclk.hw.vco / 2; in bxt_sanitize_cdclk()
1851 clock = dev_priv->display.cdclk.hw.cdclk; in bxt_sanitize_cdclk()
1854 dev_priv->display.cdclk.hw.vco); in bxt_sanitize_cdclk()
1861 dev_priv->display.cdclk.hw.cdclk >= 500000) in bxt_sanitize_cdclk()
1872 dev_priv->display.cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
1875 dev_priv->display.cdclk.hw.vco = -1; in bxt_sanitize_cdclk()
1884 if (dev_priv->display.cdclk.hw.cdclk != 0 && in bxt_cdclk_init_hw()
1885 dev_priv->display.cdclk.hw.vco != 0) in bxt_cdclk_init_hw()
1888 cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_init_hw()
1905 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_uninit_hw()
1919 * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and
1921 * during the display core initialization sequence, after which the DMC will
1936 * Uninitialize CDCLK. This is done only during the display core
2080 if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config)) in intel_set_cdclk()
2083 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk)) in intel_set_cdclk()
2101 mutex_lock(&dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2106 &dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2116 mutex_unlock(&dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2127 intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config), in intel_set_cdclk()
2129 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]"); in intel_set_cdclk()
2248 /* Display WA #1145: glk */ in intel_crtc_compute_min_cdclk()
2251 /* Display WA #1144: skl,bxt */ in intel_crtc_compute_min_cdclk()
2318 dev_priv->display.cdclk.max_cdclk_freq)); in intel_crtc_compute_min_cdclk()
2371 if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) { in intel_compute_min_cdclk()
2374 min_cdclk, dev_priv->display.cdclk.max_cdclk_freq); in intel_compute_min_cdclk()
2646 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj); in intel_atomic_get_cdclk_state()
2696 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, in intel_cdclk_init()
2802 int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq; in intel_compute_max_dotclk()
2828 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
2829 dev_priv->display.cdclk.max_cdclk_freq = 552000; in intel_update_max_cdclk()
2831 dev_priv->display.cdclk.max_cdclk_freq = 556800; in intel_update_max_cdclk()
2833 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
2834 dev_priv->display.cdclk.max_cdclk_freq = 648000; in intel_update_max_cdclk()
2836 dev_priv->display.cdclk.max_cdclk_freq = 652800; in intel_update_max_cdclk()
2838 dev_priv->display.cdclk.max_cdclk_freq = 316800; in intel_update_max_cdclk()
2840 dev_priv->display.cdclk.max_cdclk_freq = 624000; in intel_update_max_cdclk()
2862 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()
2871 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
2873 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
2875 dev_priv->display.cdclk.max_cdclk_freq = 540000; in intel_update_max_cdclk()
2877 dev_priv->display.cdclk.max_cdclk_freq = 675000; in intel_update_max_cdclk()
2879 dev_priv->display.cdclk.max_cdclk_freq = 320000; in intel_update_max_cdclk()
2881 dev_priv->display.cdclk.max_cdclk_freq = 400000; in intel_update_max_cdclk()
2884 dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk; in intel_update_max_cdclk()
2890 dev_priv->display.cdclk.max_cdclk_freq); in intel_update_max_cdclk()
2904 intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw); in intel_update_cdclk()
2914 DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000)); in intel_update_cdclk()
3197 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3198 dev_priv->display.cdclk.table = dg2_cdclk_table; in intel_init_cdclk_hooks()
3200 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3203 dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; in intel_init_cdclk_hooks()
3205 dev_priv->display.cdclk.table = adlp_cdclk_table; in intel_init_cdclk_hooks()
3207 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3208 dev_priv->display.cdclk.table = rkl_cdclk_table; in intel_init_cdclk_hooks()
3210 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3211 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3213 dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs; in intel_init_cdclk_hooks()
3214 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3216 dev_priv->display.funcs.cdclk = &icl_cdclk_funcs; in intel_init_cdclk_hooks()
3217 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3219 dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs; in intel_init_cdclk_hooks()
3221 dev_priv->display.cdclk.table = glk_cdclk_table; in intel_init_cdclk_hooks()
3223 dev_priv->display.cdclk.table = bxt_cdclk_table; in intel_init_cdclk_hooks()
3225 dev_priv->display.funcs.cdclk = &skl_cdclk_funcs; in intel_init_cdclk_hooks()
3227 dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs; in intel_init_cdclk_hooks()
3229 dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs; in intel_init_cdclk_hooks()
3231 dev_priv->display.funcs.cdclk = &chv_cdclk_funcs; in intel_init_cdclk_hooks()
3233 dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs; in intel_init_cdclk_hooks()
3235 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3237 dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs; in intel_init_cdclk_hooks()
3239 dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs; in intel_init_cdclk_hooks()
3241 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3243 dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs; in intel_init_cdclk_hooks()
3245 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3247 dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs; in intel_init_cdclk_hooks()
3249 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3251 dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs; in intel_init_cdclk_hooks()
3253 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3255 dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs; in intel_init_cdclk_hooks()
3257 dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs; in intel_init_cdclk_hooks()
3259 dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs; in intel_init_cdclk_hooks()
3261 dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs; in intel_init_cdclk_hooks()
3263 dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs; in intel_init_cdclk_hooks()
3265 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()
3268 if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk, in intel_init_cdclk_hooks()
3270 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()