Lines Matching defs:mipi_config

97 struct mipi_config {  struct
98 	u16 panel_id;
101 	u32 enable_dithering:1;
102 	u32 rsvd1:1;
103 	u32 is_bridge:1;
105 	u32 panel_arch_type:2;
106 	u32 is_cmd_mode:1;
111 	u32 video_transfer_mode:2;
113 	u32 cabc_supported:1;
116 	u32 pwm_blc:1;
123 	u32 videomode_color_format:4;
130 	u32 rotation:2;
131 	u32 bta_enabled:1;
132 	u32 rsvd2:15;
138 	u16 dual_link:2;
139 	u16 lane_cnt:2;
140 	u16 pixel_overlap:3;
141 	u16 rgb_flip:1;
145 	u16 dl_dcs_cabc_ports:2;
146 	u16 dl_dcs_backlight_ports:2;
147 	u16 rsvd3:4;
149 	u16 rsvd4;
151 	u8 rsvd5;
152 	u32 target_burst_mode_freq;
153 	u32 dsi_ddr_clk;
154 	u32 bridge_ref_clk;
159 	u8 byte_clk_sel:2;
161 	u8 rsvd6:6;
164 	u16 dphy_param_valid:1;
165 	u16 eot_pkt_disabled:1;
166 	u16 enable_clk_stop:1;
167 	u16 rsvd7:13;
169 	u32 hs_tx_timeout;
170 	u32 lp_rx_timeout;
171 	u32 turn_around_timeout;
172 	u32 device_reset_timer;
173 	u32 master_init_timer;
174 	u32 dbi_bw_timer;
175 	u32 lp_byte_clk_val;
178 	u32 prepare_cnt:6;
179 	u32 rsvd8:2;
180 	u32 clk_zero_cnt:8;
181 	u32 trail_cnt:5;
182 	u32 rsvd9:3;
183 	u32 exit_zero_cnt:6;
184 	u32 rsvd10:2;
186 	u32 clk_lane_switch_cnt;
187 	u32 hl_switch_cnt;
189 	u32 rsvd11[6];
192 	u8 tclk_miss;
193 	u8 tclk_post;
194 	u8 rsvd12;
195 	u8 tclk_pre;
196 	u8 tclk_prepare;
197 	u8 tclk_settle;
198 	u8 tclk_term_enable;
199 	u8 tclk_trail;
200 	u16 tclk_prepare_clkzero;
201 	u8 rsvd13;
202 	u8 td_term_enable;
203 	u8 teot;
204 	u8 ths_exit;
205 	u8 ths_prepare;
206 	u16 ths_prepare_hszero;
207 	u8 rsvd14;
208 	u8 ths_settle;
209 	u8 ths_skip;
210 	u8 ths_trail;
211 	u8 tinit;
212 	u8 tlpx;
213 	u8 rsvd15[3];
216 	u8 panel_enable;
217 	u8 bl_enable;
218 	u8 pwm_enable;
219 	u8 reset_r_n;
220 	u8 pwr_down_r;
221 	u8 stdby_r_n;