Lines Matching +full:mipi +full:- +full:dsi1
69 drm_err(&dev_priv->drm, "DSI header credits not released\n"); in wait_for_header_credits()
81 drm_err(&dev_priv->drm, "DSI payload credits not released\n"); in wait_for_payload_credits()
98 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in wait_for_cmds_dispatched_to_panel()
106 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
113 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
114 dsi = intel_dsi->dsi_hosts[port]->device; in wait_for_cmds_dispatched_to_panel()
115 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in wait_for_cmds_dispatched_to_panel()
116 dsi->channel = 0; in wait_for_cmds_dispatched_to_panel()
119 drm_err(&dev_priv->drm, in wait_for_cmds_dispatched_to_panel()
124 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
130 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
134 drm_err(&dev_priv->drm, "LPTX bit not cleared\n"); in wait_for_cmds_dispatched_to_panel()
141 struct intel_dsi *intel_dsi = host->intel_dsi; in dsi_send_pkt_payld()
142 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); in dsi_send_pkt_payld()
143 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); in dsi_send_pkt_payld()
144 const u8 *data = packet->payload; in dsi_send_pkt_payld()
145 u32 len = packet->payload_length; in dsi_send_pkt_payld()
150 drm_err(&i915->drm, "payload size exceeds max queue limit\n"); in dsi_send_pkt_payld()
151 return -EINVAL; in dsi_send_pkt_payld()
158 return -EBUSY; in dsi_send_pkt_payld()
160 for (j = 0; j < min_t(u32, len - i, 4); j++) in dsi_send_pkt_payld()
173 struct intel_dsi *intel_dsi = host->intel_dsi; in dsi_send_pkt_hdr()
174 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); in dsi_send_pkt_hdr()
175 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); in dsi_send_pkt_hdr()
179 return -EBUSY; in dsi_send_pkt_hdr()
183 if (packet->payload) in dsi_send_pkt_hdr()
196 tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT); in dsi_send_pkt_hdr()
197 tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT); in dsi_send_pkt_hdr()
198 tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT); in dsi_send_pkt_hdr()
199 tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT); in dsi_send_pkt_hdr()
207 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in icl_dsi_frame_update()
208 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in icl_dsi_frame_update()
212 mode_flags = crtc_state->mode_flags; in icl_dsi_frame_update()
233 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in dsi_program_swing_and_deemphasis()
239 for_each_dsi_phy(phy, intel_dsi->phys) { in dsi_program_swing_and_deemphasis()
241 * Program voltage swing and pre-emphasis level values as per in dsi_program_swing_and_deemphasis()
300 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in configure_dual_link_mode()
307 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); in configure_dual_link_mode()
309 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { in configure_dual_link_mode()
311 &pipe_config->hw.adjusted_mode; in configure_dual_link_mode()
313 u16 hactive = adjusted_mode->crtc_hdisplay; in configure_dual_link_mode()
317 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; in configure_dual_link_mode()
320 drm_err(&dev_priv->drm, in configure_dual_link_mode()
344 if (crtc_state->dsc.compression_enable) in afe_clk()
345 bpp = crtc_state->dsc.compressed_bpp; in afe_clk()
347 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in afe_clk()
349 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); in afe_clk()
355 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_program_esc_clk_div()
368 esc_clk_div_m_phy = (act_word_clk - 1) / 2; in gen11_dsi_program_esc_clk_div()
373 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_program_esc_clk_div()
379 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_program_esc_clk_div()
386 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_program_esc_clk_div()
399 for_each_dsi_port(port, intel_dsi->ports) { in get_dsi_io_power_domains()
400 drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]); in get_dsi_io_power_domains()
401 intel_dsi->io_wakeref[port] = in get_dsi_io_power_domains()
411 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_enable_io_power()
416 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_enable_io_power()
427 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_power_up_lanes()
431 for_each_dsi_phy(phy, intel_dsi->phys) in gen11_dsi_power_up_lanes()
433 intel_dsi->lane_count, false); in gen11_dsi_power_up_lanes()
438 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_config_phy_lanes_sequence()
445 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_config_phy_lanes_sequence()
461 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_config_phy_lanes_sequence()
493 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_voltage_swing_program_seq()
499 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_voltage_swing_program_seq()
513 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_voltage_swing_program_seq()
520 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_voltage_swing_program_seq()
529 /* Program swing and de-emphasis */ in gen11_dsi_voltage_swing_program_seq()
533 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_voltage_swing_program_seq()
545 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_enable_ddi_buffer()
550 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_enable_ddi_buffer()
558 drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", in gen11_dsi_enable_ddi_buffer()
567 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_setup_dphy_timings()
573 /* Program T-INIT master registers */ in gen11_dsi_setup_dphy_timings()
574 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_setup_dphy_timings()
577 tmp |= intel_dsi->init_count; in gen11_dsi_setup_dphy_timings()
582 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_setup_dphy_timings()
584 intel_dsi->dphy_reg); in gen11_dsi_setup_dphy_timings()
588 intel_dsi->dphy_reg); in gen11_dsi_setup_dphy_timings()
592 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_setup_dphy_timings()
594 intel_dsi->dphy_data_lane_reg); in gen11_dsi_setup_dphy_timings()
598 intel_dsi->dphy_data_lane_reg); in gen11_dsi_setup_dphy_timings()
609 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_setup_dphy_timings()
630 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_setup_dphy_timings()
640 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_gate_clocks()
645 mutex_lock(&dev_priv->display.dpll.lock); in gen11_dsi_gate_clocks()
647 for_each_dsi_phy(phy, intel_dsi->phys) in gen11_dsi_gate_clocks()
651 mutex_unlock(&dev_priv->display.dpll.lock); in gen11_dsi_gate_clocks()
656 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_ungate_clocks()
661 mutex_lock(&dev_priv->display.dpll.lock); in gen11_dsi_ungate_clocks()
663 for_each_dsi_phy(phy, intel_dsi->phys) in gen11_dsi_ungate_clocks()
667 mutex_unlock(&dev_priv->display.dpll.lock); in gen11_dsi_ungate_clocks()
672 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_is_clock_enabled()
680 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_is_clock_enabled()
691 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_map_pll()
693 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in gen11_dsi_map_pll()
697 mutex_lock(&dev_priv->display.dpll.lock); in gen11_dsi_map_pll()
700 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_map_pll()
702 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); in gen11_dsi_map_pll()
706 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_map_pll()
713 mutex_unlock(&dev_priv->display.dpll.lock); in gen11_dsi_map_pll()
720 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_configure_transcoder()
722 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in gen11_dsi_configure_transcoder()
723 enum pipe pipe = crtc->pipe; in gen11_dsi_configure_transcoder()
728 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_configure_transcoder()
732 if (intel_dsi->eotp_pkt) in gen11_dsi_configure_transcoder()
745 if (intel_dsi->clock_stop) in gen11_dsi_configure_transcoder()
759 if (intel_dsi->bgr_enabled) in gen11_dsi_configure_transcoder()
764 if (pipe_config->dsc.compression_enable) { in gen11_dsi_configure_transcoder()
767 switch (intel_dsi->pixel_format) { in gen11_dsi_configure_transcoder()
769 MISSING_CASE(intel_dsi->pixel_format); in gen11_dsi_configure_transcoder()
794 switch (intel_dsi->video_mode) { in gen11_dsi_configure_transcoder()
796 MISSING_CASE(intel_dsi->video_mode); in gen11_dsi_configure_transcoder()
823 if (intel_dsi->dual_link) { in gen11_dsi_configure_transcoder()
824 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_configure_transcoder()
837 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_configure_transcoder()
843 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); in gen11_dsi_configure_transcoder()
871 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_configure_transcoder()
875 drm_err(&dev_priv->drm, "DSI link not ready\n"); in gen11_dsi_configure_transcoder()
883 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_set_transcoder_timings()
886 &crtc_state->hw.adjusted_mode; in gen11_dsi_set_transcoder_timings()
901 * non-compressed link speeds, and simplifies down to the ratio between in gen11_dsi_set_transcoder_timings()
902 * compressed and non-compressed bpp. in gen11_dsi_set_transcoder_timings()
904 if (crtc_state->dsc.compression_enable) { in gen11_dsi_set_transcoder_timings()
905 mul = crtc_state->dsc.compressed_bpp; in gen11_dsi_set_transcoder_timings()
906 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in gen11_dsi_set_transcoder_timings()
909 hactive = adjusted_mode->crtc_hdisplay; in gen11_dsi_set_transcoder_timings()
912 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); in gen11_dsi_set_transcoder_timings()
916 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); in gen11_dsi_set_transcoder_timings()
917 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); in gen11_dsi_set_transcoder_timings()
918 hsync_size = hsync_end - hsync_start; in gen11_dsi_set_transcoder_timings()
919 hback_porch = (adjusted_mode->crtc_htotal - in gen11_dsi_set_transcoder_timings()
920 adjusted_mode->crtc_hsync_end); in gen11_dsi_set_transcoder_timings()
921 vactive = adjusted_mode->crtc_vdisplay; in gen11_dsi_set_transcoder_timings()
924 vtotal = adjusted_mode->crtc_vtotal; in gen11_dsi_set_transcoder_timings()
928 if (crtc_state->dsc.compression_enable) in gen11_dsi_set_transcoder_timings()
929 bpp = crtc_state->dsc.compressed_bpp; in gen11_dsi_set_transcoder_timings()
931 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in gen11_dsi_set_transcoder_timings()
934 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); in gen11_dsi_set_transcoder_timings()
937 vsync_start = adjusted_mode->crtc_vsync_start; in gen11_dsi_set_transcoder_timings()
938 vsync_end = adjusted_mode->crtc_vsync_end; in gen11_dsi_set_transcoder_timings()
939 vsync_shift = hsync_start - htotal / 2; in gen11_dsi_set_transcoder_timings()
941 if (intel_dsi->dual_link) { in gen11_dsi_set_transcoder_timings()
943 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) in gen11_dsi_set_transcoder_timings()
944 hactive += intel_dsi->pixel_overlap; in gen11_dsi_set_transcoder_timings()
949 if (adjusted_mode->crtc_hdisplay < 256) in gen11_dsi_set_transcoder_timings()
950 drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n"); in gen11_dsi_set_transcoder_timings()
953 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) in gen11_dsi_set_transcoder_timings()
954 drm_err(&dev_priv->drm, in gen11_dsi_set_transcoder_timings()
958 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
961 (hactive - 1) | ((htotal - 1) << 16)); in gen11_dsi_set_transcoder_timings()
966 if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) { in gen11_dsi_set_transcoder_timings()
969 drm_err(&dev_priv->drm, in gen11_dsi_set_transcoder_timings()
974 drm_err(&dev_priv->drm, "hback porch < 16 pixels\n"); in gen11_dsi_set_transcoder_timings()
976 if (intel_dsi->dual_link) { in gen11_dsi_set_transcoder_timings()
981 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
984 (hsync_start - 1) | ((hsync_end - 1) << 16)); in gen11_dsi_set_transcoder_timings()
989 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
993 * non-interlaced info from VBT is not saved inside in gen11_dsi_set_transcoder_timings()
998 (vactive - 1) | ((vtotal - 1) << 16)); in gen11_dsi_set_transcoder_timings()
1002 drm_err(&dev_priv->drm, "Invalid vsync_end value\n"); in gen11_dsi_set_transcoder_timings()
1005 drm_err(&dev_priv->drm, "vsync_start less than vactive\n"); in gen11_dsi_set_transcoder_timings()
1009 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
1012 (vsync_start - 1) | ((vsync_end - 1) << 16)); in gen11_dsi_set_transcoder_timings()
1023 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
1032 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
1035 (vactive - 1) | ((vtotal - 1) << 16)); in gen11_dsi_set_transcoder_timings()
1042 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_enable_transcoder()
1048 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_enable_transcoder()
1057 drm_err(&dev_priv->drm, in gen11_dsi_enable_transcoder()
1065 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_setup_timeouts()
1080 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, in gen11_dsi_setup_timeouts()
1082 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); in gen11_dsi_setup_timeouts()
1083 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); in gen11_dsi_setup_timeouts()
1085 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_setup_timeouts()
1115 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_config_util_pin()
1121 * for dual link/DSI1 TE is from slave DSI1 in gen11_dsi_config_util_pin()
1124 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) in gen11_dsi_config_util_pin()
1145 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ in gen11_dsi_enable_port_and_phy()
1154 /* setup D-PHY timings */ in gen11_dsi_enable_port_and_phy()
1172 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_powerup_panel()
1181 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_powerup_panel()
1192 dsi = intel_dsi->dsi_hosts[port]->device; in gen11_dsi_powerup_panel()
1195 drm_err(&dev_priv->drm, in gen11_dsi_powerup_panel()
1199 /* panel power on related mipi dsi vbt sequences */ in gen11_dsi_powerup_panel()
1201 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); in gen11_dsi_powerup_panel()
1244 * When pipe A is disabled and MIPI DSI is enabled on pipe B,
1252 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in icl_apply_kvmr_pipe_a_wa()
1261 * Wa_16012360555:adl-p
1268 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in adlp_set_lp_hs_wakeup_gb()
1273 for_each_dsi_port(port, intel_dsi->ports) in adlp_set_lp_hs_wakeup_gb()
1286 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); in gen11_dsi_enable()
1288 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); in gen11_dsi_enable()
1291 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true); in gen11_dsi_enable()
1293 /* Wa_16012360555:adl-p */ in gen11_dsi_enable()
1308 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_disable_transcoder()
1314 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_disable_transcoder()
1325 drm_err(&dev_priv->drm, in gen11_dsi_disable_transcoder()
1344 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_deconfigure_trancoder()
1352 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_deconfigure_trancoder()
1360 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_deconfigure_trancoder()
1370 drm_err(&dev_priv->drm, "DSI link not in ULPS\n"); in gen11_dsi_deconfigure_trancoder()
1374 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_deconfigure_trancoder()
1382 if (intel_dsi->dual_link) { in gen11_dsi_deconfigure_trancoder()
1383 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_deconfigure_trancoder()
1396 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_disable_port()
1402 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_disable_port()
1410 drm_err(&dev_priv->drm, in gen11_dsi_disable_port()
1419 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_disable_io_power()
1424 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_disable_io_power()
1427 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); in gen11_dsi_disable_io_power()
1436 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_disable_io_power()
1449 struct intel_crtc *crtc = to_intel_crtc(old_conn_state->crtc); in gen11_dsi_disable()
1459 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false); in gen11_dsi_disable()
1500 &pipe_config->hw.adjusted_mode; in gen11_dsi_get_timings()
1502 if (pipe_config->dsc.compressed_bpp) { in gen11_dsi_get_timings()
1503 int div = pipe_config->dsc.compressed_bpp; in gen11_dsi_get_timings()
1504 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in gen11_dsi_get_timings()
1506 adjusted_mode->crtc_htotal = in gen11_dsi_get_timings()
1507 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); in gen11_dsi_get_timings()
1508 adjusted_mode->crtc_hsync_start = in gen11_dsi_get_timings()
1509 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); in gen11_dsi_get_timings()
1510 adjusted_mode->crtc_hsync_end = in gen11_dsi_get_timings()
1511 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); in gen11_dsi_get_timings()
1514 if (intel_dsi->dual_link) { in gen11_dsi_get_timings()
1515 adjusted_mode->crtc_hdisplay *= 2; in gen11_dsi_get_timings()
1516 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) in gen11_dsi_get_timings()
1517 adjusted_mode->crtc_hdisplay -= in gen11_dsi_get_timings()
1518 intel_dsi->pixel_overlap; in gen11_dsi_get_timings()
1519 adjusted_mode->crtc_htotal *= 2; in gen11_dsi_get_timings()
1521 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; in gen11_dsi_get_timings()
1522 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; in gen11_dsi_get_timings()
1524 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { in gen11_dsi_get_timings()
1525 if (intel_dsi->dual_link) { in gen11_dsi_get_timings()
1526 adjusted_mode->crtc_hsync_start *= 2; in gen11_dsi_get_timings()
1527 adjusted_mode->crtc_hsync_end *= 2; in gen11_dsi_get_timings()
1530 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; in gen11_dsi_get_timings()
1531 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; in gen11_dsi_get_timings()
1536 struct drm_device *dev = intel_dsi->base.base.dev; in gen11_dsi_is_periodic_cmd_mode()
1541 if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_is_periodic_cmd_mode()
1553 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) in gen11_dsi_get_cmd_mode_config()
1554 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 | in gen11_dsi_get_cmd_mode_config()
1556 else if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_get_cmd_mode_config()
1557 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1; in gen11_dsi_get_cmd_mode_config()
1559 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0; in gen11_dsi_get_cmd_mode_config()
1565 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in gen11_dsi_get_config()
1570 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; in gen11_dsi_get_config()
1571 if (intel_dsi->dual_link) in gen11_dsi_get_config()
1572 pipe_config->hw.adjusted_mode.crtc_clock *= 2; in gen11_dsi_get_config()
1575 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); in gen11_dsi_get_config()
1576 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); in gen11_dsi_get_config()
1583 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE; in gen11_dsi_get_config()
1589 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_sync_state()
1596 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); in gen11_dsi_sync_state()
1597 pipe = intel_crtc->pipe; in gen11_dsi_sync_state()
1602 drm_dbg_kms(&dev_priv->drm, in gen11_dsi_sync_state()
1604 encoder->base.base.id, in gen11_dsi_sync_state()
1605 encoder->base.name); in gen11_dsi_sync_state()
1611 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_dsc_compute_config()
1612 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in gen11_dsi_dsc_compute_config()
1621 if (crtc_state->pipe_bpp < 8 * 3) in gen11_dsi_dsc_compute_config()
1622 return -EINVAL; in gen11_dsi_dsc_compute_config()
1625 if (crtc_state->dsc.slice_count > 1) in gen11_dsi_dsc_compute_config()
1626 crtc_state->dsc.dsc_split = true; in gen11_dsi_dsc_compute_config()
1628 vdsc_cfg->convert_rgb = true; in gen11_dsi_dsc_compute_config()
1631 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; in gen11_dsi_dsc_compute_config()
1633 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; in gen11_dsi_dsc_compute_config()
1640 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); in gen11_dsi_dsc_compute_config()
1641 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); in gen11_dsi_dsc_compute_config()
1642 drm_WARN_ON(&dev_priv->drm, in gen11_dsi_dsc_compute_config()
1643 vdsc_cfg->pic_width % vdsc_cfg->slice_width); in gen11_dsi_dsc_compute_config()
1644 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8); in gen11_dsi_dsc_compute_config()
1645 drm_WARN_ON(&dev_priv->drm, in gen11_dsi_dsc_compute_config()
1646 vdsc_cfg->pic_height % vdsc_cfg->slice_height); in gen11_dsi_dsc_compute_config()
1652 crtc_state->dsc.compression_enable = true; in gen11_dsi_dsc_compute_config()
1661 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in gen11_dsi_compute_config()
1664 struct intel_connector *intel_connector = intel_dsi->attached_connector; in gen11_dsi_compute_config()
1666 &pipe_config->hw.adjusted_mode; in gen11_dsi_compute_config()
1669 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in gen11_dsi_compute_config()
1679 adjusted_mode->flags = 0; in gen11_dsi_compute_config()
1682 if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_compute_config()
1683 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; in gen11_dsi_compute_config()
1685 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; in gen11_dsi_compute_config()
1687 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) in gen11_dsi_compute_config()
1688 pipe_config->pipe_bpp = 24; in gen11_dsi_compute_config()
1690 pipe_config->pipe_bpp = 18; in gen11_dsi_compute_config()
1692 pipe_config->clock_set = true; in gen11_dsi_compute_config()
1695 drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n"); in gen11_dsi_compute_config()
1697 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; in gen11_dsi_compute_config()
1713 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in gen11_dsi_get_power_domains()
1722 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_get_hw_state()
1731 encoder->power_domain); in gen11_dsi_get_hw_state()
1735 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_get_hw_state()
1752 drm_err(&dev_priv->drm, "Invalid PIPE input\n"); in gen11_dsi_get_hw_state()
1760 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in gen11_dsi_get_hw_state()
1767 if (crtc_state->dsc.compression_enable) { in gen11_dsi_initial_fastset_check()
1768 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n"); in gen11_dsi_initial_fastset_check()
1769 crtc_state->uapi.mode_changed = true; in gen11_dsi_initial_fastset_check()
1828 if (msg->flags & MIPI_DSI_MSG_USE_LPM) in gen11_dsi_host_transfer()
1832 if (mipi_dsi_packet_format_is_long(msg->type)) { in gen11_dsi_host_transfer()
1866 struct drm_device *dev = intel_dsi->base.base.dev; in icl_dphy_param_init()
1868 struct intel_connector *connector = intel_dsi->attached_connector; in icl_dphy_param_init()
1869 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; in icl_dphy_param_init()
1878 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); in icl_dphy_param_init()
1879 ths_prepare_ns = max(mipi_config->ths_prepare, in icl_dphy_param_init()
1880 mipi_config->tclk_prepare); in icl_dphy_param_init()
1891 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n", in icl_dphy_param_init()
1897 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - in icl_dphy_param_init()
1900 drm_dbg_kms(&dev_priv->drm, in icl_dphy_param_init()
1908 drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", in icl_dphy_param_init()
1914 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); in icl_dphy_param_init()
1916 drm_dbg_kms(&dev_priv->drm, in icl_dphy_param_init()
1922 tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns); in icl_dphy_param_init()
1924 drm_dbg_kms(&dev_priv->drm, in icl_dphy_param_init()
1931 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - in icl_dphy_param_init()
1934 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n", in icl_dphy_param_init()
1940 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); in icl_dphy_param_init()
1942 drm_dbg_kms(&dev_priv->drm, in icl_dphy_param_init()
1949 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | in icl_dphy_param_init()
1961 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | in icl_dphy_param_init()
1983 drm_connector_attach_scaling_mode_property(&connector->base, in icl_dsi_add_properties()
1986 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; in icl_dsi_add_properties()
1988 drm_connector_set_panel_orientation_with_quirk(&connector->base, in icl_dsi_add_properties()
1990 fixed_mode->hdisplay, in icl_dsi_add_properties()
1991 fixed_mode->vdisplay); in icl_dsi_add_properties()
1996 struct drm_device *dev = &dev_priv->drm; in icl_dsi_init()
2016 encoder = &intel_dsi->base; in icl_dsi_init()
2017 intel_dsi->attached_connector = intel_connector; in icl_dsi_init()
2018 connector = &intel_connector->base; in icl_dsi_init()
2021 drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs, in icl_dsi_init()
2024 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; in icl_dsi_init()
2025 encoder->pre_enable = gen11_dsi_pre_enable; in icl_dsi_init()
2026 encoder->enable = gen11_dsi_enable; in icl_dsi_init()
2027 encoder->disable = gen11_dsi_disable; in icl_dsi_init()
2028 encoder->post_disable = gen11_dsi_post_disable; in icl_dsi_init()
2029 encoder->port = port; in icl_dsi_init()
2030 encoder->get_config = gen11_dsi_get_config; in icl_dsi_init()
2031 encoder->sync_state = gen11_dsi_sync_state; in icl_dsi_init()
2032 encoder->update_pipe = intel_backlight_update; in icl_dsi_init()
2033 encoder->compute_config = gen11_dsi_compute_config; in icl_dsi_init()
2034 encoder->get_hw_state = gen11_dsi_get_hw_state; in icl_dsi_init()
2035 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check; in icl_dsi_init()
2036 encoder->type = INTEL_OUTPUT_DSI; in icl_dsi_init()
2037 encoder->cloneable = 0; in icl_dsi_init()
2038 encoder->pipe_mask = ~0; in icl_dsi_init()
2039 encoder->power_domain = POWER_DOMAIN_PORT_DSI; in icl_dsi_init()
2040 encoder->get_power_domains = gen11_dsi_get_power_domains; in icl_dsi_init()
2041 encoder->disable_clock = gen11_dsi_gate_clocks; in icl_dsi_init()
2042 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled; in icl_dsi_init()
2048 connector->display_info.subpixel_order = SubPixelHorizontalRGB; in icl_dsi_init()
2049 connector->interlace_allowed = false; in icl_dsi_init()
2050 connector->doublescan_allowed = false; in icl_dsi_init()
2051 intel_connector->get_hw_state = intel_connector_get_hw_state; in icl_dsi_init()
2056 intel_bios_init_panel(dev_priv, &intel_connector->panel, NULL, NULL); in icl_dsi_init()
2058 mutex_lock(&dev->mode_config.mutex); in icl_dsi_init()
2060 mutex_unlock(&dev->mode_config.mutex); in icl_dsi_init()
2063 drm_err(&dev_priv->drm, "DSI fixed mode info missing\n"); in icl_dsi_init()
2071 if (intel_connector->panel.vbt.dsi.config->dual_link) in icl_dsi_init()
2072 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); in icl_dsi_init()
2074 intel_dsi->ports = BIT(port); in icl_dsi_init()
2076 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) in icl_dsi_init()
2077 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; in icl_dsi_init()
2079 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) in icl_dsi_init()
2080 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; in icl_dsi_init()
2082 for_each_dsi_port(port, intel_dsi->ports) { in icl_dsi_init()
2089 intel_dsi->dsi_hosts[port] = host; in icl_dsi_init()
2093 drm_dbg_kms(&dev_priv->drm, "no device found\n"); in icl_dsi_init()
2104 drm_encoder_cleanup(&encoder->base); in icl_dsi_init()