108 			       enum i9xx_plane_id i9xx_plane)  in i9xx_plane_has_fbc()  argument
114 		return i9xx_plane == PLANE_A; /* tied to pipe A */  in i9xx_plane_has_fbc()
116 		return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||  in i9xx_plane_has_fbc()
117 			i9xx_plane == PLANE_C;  in i9xx_plane_has_fbc()
119 		return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;  in i9xx_plane_has_fbc()
121 		return i9xx_plane == PLANE_A;  in i9xx_plane_has_fbc()
125 					enum i9xx_plane_id i9xx_plane)  in i9xx_plane_fbc()  argument
127 	if (i9xx_plane_has_fbc(dev_priv, i9xx_plane))  in i9xx_plane_fbc()
136 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;  in i9xx_plane_has_windowing()  local
139 		return i9xx_plane == PLANE_B;  in i9xx_plane_has_windowing()
143 		return i9xx_plane == PLANE_C;  in i9xx_plane_has_windowing()
145 		return i9xx_plane == PLANE_B ||  in i9xx_plane_has_windowing()
146 			i9xx_plane == PLANE_C;  in i9xx_plane_has_windowing()
420 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;  in i9xx_plane_update_noarm()  local
422 	intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),  in i9xx_plane_update_noarm()
436 		intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),  in i9xx_plane_update_noarm()
438 		intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),  in i9xx_plane_update_noarm()
448 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;  in i9xx_plane_update_arm()  local
462 	if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {  in i9xx_plane_update_arm()
468 		intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),  in i9xx_plane_update_arm()
470 		intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),  in i9xx_plane_update_arm()
472 		intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);  in i9xx_plane_update_arm()
476 		intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),  in i9xx_plane_update_arm()
479 		intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),  in i9xx_plane_update_arm()
481 		intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),  in i9xx_plane_update_arm()
490 	intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);  in i9xx_plane_update_arm()
493 		intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),  in i9xx_plane_update_arm()
496 		intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),  in i9xx_plane_update_arm()
518 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;  in i9xx_plane_disable_arm()  local
533 	intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);  in i9xx_plane_disable_arm()
536 		intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);  in i9xx_plane_disable_arm()
538 		intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0);  in i9xx_plane_disable_arm()
550 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;  in g4x_primary_async_flip()  local
555 	intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);  in g4x_primary_async_flip()
557 	intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),  in g4x_primary_async_flip()
569 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;  in vlv_primary_async_flip()  local
571 	intel_de_write_fw(dev_priv, DSPADDR_VLV(i9xx_plane),  in vlv_primary_async_flip()
603 	ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));  in ivb_primary_enable_flip_done()
613 	ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));  in ivb_primary_disable_flip_done()
623 	ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane));  in ilk_primary_enable_flip_done()
633 	ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane));  in ilk_primary_disable_flip_done()
664 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;  in i9xx_plane_get_hw_state()  local
679 	val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));  in i9xx_plane_get_hw_state()
748 		if (plane->i9xx_plane == PLANE_C)  in i9xx_plane_max_stride()
795 		plane->i9xx_plane = (enum i9xx_plane_id) !pipe;  in intel_primary_plane_create()
797 		plane->i9xx_plane = (enum i9xx_plane_id) pipe;  in intel_primary_plane_create()
801 	intel_fbc_add_plane(i9xx_plane_fbc(dev_priv, plane->i9xx_plane), plane);  in intel_primary_plane_create()
903 					       plane_name(plane->i9xx_plane));  in intel_primary_plane_create()
979 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;  in i9xx_get_initial_plane_config()  local
1002 	val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));  in i9xx_get_initial_plane_config()
1023 		offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));  in i9xx_get_initial_plane_config()
1024 		base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK;  in i9xx_get_initial_plane_config()
1028 					       DSPTILEOFF(i9xx_plane));  in i9xx_get_initial_plane_config()
1031 					       DSPLINOFF(i9xx_plane));  in i9xx_get_initial_plane_config()
1032 		base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK;  in i9xx_get_initial_plane_config()
1034 		base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));  in i9xx_get_initial_plane_config()
1042 	val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));  in i9xx_get_initial_plane_config()