1 // SPDX-License-Identifier: MIT
15 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_ips_enable()
16 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in hsw_ips_enable()
18 	if (!crtc_state->ips_enabled)  in hsw_ips_enable()
22 	 * We can only enable IPS after we enable a plane and wait for a vblank  in hsw_ips_enable()
24 	 * a vblank wait.  in hsw_ips_enable()
26 	drm_WARN_ON(&i915->drm,  in hsw_ips_enable()
27 		    !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));  in hsw_ips_enable()
30 		drm_WARN_ON(&i915->drm,  in hsw_ips_enable()
31 			    snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL,  in hsw_ips_enable()
36 		 * mailbox." Moreover, the mailbox may return a bogus state,  in hsw_ips_enable()
42 		 * The bit only becomes 1 in the next vblank, so this wait here  in hsw_ips_enable()
44 		 * and don't wait for vblanks until the end of crtc_enable, then  in hsw_ips_enable()
45 		 * the HW state readout code will complain that the expected  in hsw_ips_enable()
49 			drm_err(&i915->drm,  in hsw_ips_enable()
56 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_ips_disable()
57 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in hsw_ips_disable()
60 	if (!crtc_state->ips_enabled)  in hsw_ips_disable()
64 		drm_WARN_ON(&i915->drm,  in hsw_ips_disable()
65 			    snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL, 0));  in hsw_ips_disable()
67 		 * Wait for PCODE to finish disabling IPS. The BSpec specified  in hsw_ips_disable()
72 			drm_err(&i915->drm,  in hsw_ips_disable()
79 	/* We need to wait for a vblank before we can disable the plane. */  in hsw_ips_disable()
85 static bool hsw_ips_need_disable(struct intel_atomic_state *state,  in hsw_ips_need_disable()  argument
88 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in hsw_ips_need_disable()
90 		intel_atomic_get_old_crtc_state(state, crtc);  in hsw_ips_need_disable()
92 		intel_atomic_get_new_crtc_state(state, crtc);  in hsw_ips_need_disable()
94 	if (!old_crtc_state->ips_enabled)  in hsw_ips_need_disable()
107 	    (new_crtc_state->uapi.color_mgmt_changed ||  in hsw_ips_need_disable()
108 	     new_crtc_state->update_pipe) &&  in hsw_ips_need_disable()
109 	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)  in hsw_ips_need_disable()
112 	return !new_crtc_state->ips_enabled;  in hsw_ips_need_disable()
115 bool hsw_ips_pre_update(struct intel_atomic_state *state,  in hsw_ips_pre_update()  argument
119 		intel_atomic_get_old_crtc_state(state, crtc);  in hsw_ips_pre_update()
121 	if (!hsw_ips_need_disable(state, crtc))  in hsw_ips_pre_update()
127 static bool hsw_ips_need_enable(struct intel_atomic_state *state,  in hsw_ips_need_enable()  argument
130 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in hsw_ips_need_enable()
132 		intel_atomic_get_old_crtc_state(state, crtc);  in hsw_ips_need_enable()
134 		intel_atomic_get_new_crtc_state(state, crtc);  in hsw_ips_need_enable()
136 	if (!new_crtc_state->ips_enabled)  in hsw_ips_need_enable()
146 	 * Re-enable IPS after the LUT has been programmed.  in hsw_ips_need_enable()
149 	    (new_crtc_state->uapi.color_mgmt_changed ||  in hsw_ips_need_enable()
150 	     new_crtc_state->update_pipe) &&  in hsw_ips_need_enable()
151 	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)  in hsw_ips_need_enable()
158 	if (new_crtc_state->update_pipe && old_crtc_state->inherited)  in hsw_ips_need_enable()
161 	return !old_crtc_state->ips_enabled;  in hsw_ips_need_enable()
164 void hsw_ips_post_update(struct intel_atomic_state *state,  in hsw_ips_post_update()  argument
168 		intel_atomic_get_new_crtc_state(state, crtc);  in hsw_ips_post_update()
170 	if (!hsw_ips_need_enable(state, crtc))  in hsw_ips_post_update()
179 	return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;  in hsw_crtc_supports_ips()
184 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_crtc_state_ips_capable()
185 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in hsw_crtc_state_ips_capable()
191 	if (!i915->params.enable_ips)  in hsw_crtc_state_ips_capable()
194 	if (crtc_state->pipe_bpp > 24)  in hsw_crtc_state_ips_capable()
205 	    crtc_state->pixel_rate > i915->display.cdclk.max_cdclk_freq * 95 / 100)  in hsw_crtc_state_ips_capable()
211 int hsw_ips_compute_config(struct intel_atomic_state *state,  in hsw_ips_compute_config()  argument
214 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in hsw_ips_compute_config()
216 		intel_atomic_get_new_crtc_state(state, crtc);  in hsw_ips_compute_config()
218 	crtc_state->ips_enabled = false;  in hsw_ips_compute_config()
229 	if (crtc_state->crc_enabled)  in hsw_ips_compute_config()
233 	if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))  in hsw_ips_compute_config()
239 		cdclk_state = intel_atomic_get_cdclk_state(state);  in hsw_ips_compute_config()
244 		if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)  in hsw_ips_compute_config()
248 	crtc_state->ips_enabled = true;  in hsw_ips_compute_config()
255 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_ips_get_config()
256 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in hsw_ips_get_config()
262 		crtc_state->ips_enabled = intel_de_read(i915, IPS_CTL) & IPS_ENABLE;  in hsw_ips_get_config()
265 		 * We cannot readout IPS state on broadwell, set to  in hsw_ips_get_config()
266 		 * true so we can set it to a defined state on first  in hsw_ips_get_config()
269 		crtc_state->ips_enabled = true;  in hsw_ips_get_config()