Lines Matching full:write
100 * write a given register, we need to make sure CURPAGE register is set
108 #define REG_CURPAGE 0xff /* write */
113 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
121 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
124 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
125 #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
126 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
130 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
134 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
135 #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
136 #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
138 #define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
139 #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
140 #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
141 #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
142 #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
143 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
148 #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
153 #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
158 #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
167 #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
174 #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
177 #define REG_MUX_AP REG(0x00, 0x26) /* read/write */
180 #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
181 #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
184 #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
185 #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
186 #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
187 #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
188 #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
189 #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
190 #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
191 #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
192 #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
193 #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
194 #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
195 #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
196 #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
197 #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
198 #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
199 #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
200 #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
201 #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
202 #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
203 #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
204 #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
205 #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
206 #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
207 #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
208 #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
209 #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
210 #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
211 #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
212 #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
213 #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
214 #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
215 #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
216 #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
217 #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
218 #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
219 #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
220 #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
221 #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
222 #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
223 #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
224 #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
225 #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
233 #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
241 #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
242 #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
247 #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
253 #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
255 #define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
259 #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
267 #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
271 #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
274 #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
278 #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
279 #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
280 #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
281 #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
282 #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
283 #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
284 #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
285 #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
286 #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
293 #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
297 #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
303 #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
304 #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
305 #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
306 #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
307 #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
311 #define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
312 #define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
313 #define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
314 #define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
315 #define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
319 #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
325 #define REG_CA_I2S REG(0x11, 0x01) /* read/write */
328 #define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
329 #define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
330 #define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
331 #define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
332 #define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
333 #define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
334 #define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
335 #define REG_CTS_N REG(0x11, 0x0c) /* read/write */
338 #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
342 #define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
345 #define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
351 #define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
355 #define REG_TX3 REG(0x12, 0x9a) /* read/write */
356 #define REG_TX4 REG(0x12, 0x9b) /* read/write */
358 #define REG_TX33 REG(0x12, 0xb8) /* read/write */
377 #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
382 #define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
390 #define REG_CEC_ENAMODS 0xff /* read/write */
618 dev_err(&client->dev, "Fixed write buffer too small (%d)\n", in reg_write_range()
736 /* Write the default value MUX register */ in tda998x_reset()
1033 /* Write the CTS and N values */ in tda998x_configure_audio()
1046 /* Write the channel status in tda998x_configure_audio()