Lines Matching +full:hard +full:- +full:wires
1 /* SPDX-License-Identifier: GPL-2.0-only */
70 #define GMBUS3 0x510c /* data buffer bytes 3-0 */
155 * - PLL enabled
156 * - pipe enabled
157 * - LVDS/DVOB/DVOC on
256 * in DVO non-gang */
413 * Programmed value is multiplier - 1, up to 5x.
442 /* Selects pipe B for LVDS data. Must be set on pre-965. */
449 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
471 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
472 * setting for whether we are in dual-channel mode. The B3 pair will
995 * The display module returns the self-diagnostic results following
1237 #define PSB_MASK(high, low) (((1<<((high)-(low)+1))-1)<<(low))
1241 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
1268 /* 32-bit value read/written from the DPIO reg. */
1270 /* 32-bit address of the DPIO reg to be read/written. */
1337 /* Link training mode - select a suitable mode for each stage */
1353 /* Signal pre-emphasis levels, like voltages, the other end tells us what
1363 /* How many wires to use. I guess 3 was too hard */
1452 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
1470 * Attributes and VB-ID.