Lines Matching +full:0 +full:x8014
11 #define GPIOA 0x5010
12 #define GPIOB 0x5014
13 #define GPIOC 0x5018
14 #define GPIOD 0x501c
15 #define GPIOE 0x5020
16 #define GPIOF 0x5024
17 #define GPIOG 0x5028
18 #define GPIOH 0x502c
19 # define GPIO_CLOCK_DIR_MASK (1 << 0)
20 # define GPIO_CLOCK_DIR_IN (0 << 1)
27 # define GPIO_DATA_DIR_IN (0 << 9)
34 #define GMBUS0 0x5100 /* clock/port select */
35 #define GMBUS_RATE_100KHZ (0<<8)
40 #define GMBUS_PORT_DISABLED 0
49 #define GMBUS1 0x5104 /* command/status */
53 #define GMBUS_CYCLE_NONE (0<<25)
60 #define GMBUS_SLAVE_READ (1<<0)
61 #define GMBUS_SLAVE_WRITE (0<<0)
62 #define GMBUS2 0x5108 /* status */
70 #define GMBUS3 0x510c /* data buffer bytes 3-0 */
71 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
76 #define GMBUS_HW_RDY_EN (1<<0)
77 #define GMBUS5 0x5120 /* byte index */
80 #define BLC_PWM_CTL 0x61254
81 #define BLC_PWM_CTL2 0x61250
85 #define BLC_PWM_CTL_C 0x62254
86 #define BLC_PWM_CTL2_C 0x62250
94 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
103 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
104 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
106 #define I915_GCFGC 0xf0
108 #define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
112 #define I855_HPLLCC 0xc0
113 #define I855_CLOCK_CONTROL_MASK (3 << 0)
114 #define I855_CLOCK_133_200 (0 << 0)
115 #define I855_CLOCK_100_200 (1 << 0)
116 #define I855_CLOCK_100_133 (2 << 0)
117 #define I855_CLOCK_166_250 (3 << 0)
120 #define HTOTAL_A 0x60000
121 #define HBLANK_A 0x60004
122 #define HSYNC_A 0x60008
123 #define VTOTAL_A 0x6000c
124 #define VBLANK_A 0x60010
125 #define VSYNC_A 0x60014
126 #define PIPEASRC 0x6001c
127 #define BCLRPAT_A 0x60020
128 #define VSYNCSHIFT_A 0x60028
130 #define HTOTAL_B 0x61000
131 #define HBLANK_B 0x61004
132 #define HSYNC_B 0x61008
133 #define VTOTAL_B 0x6100c
134 #define VBLANK_B 0x61010
135 #define VSYNC_B 0x61014
136 #define PIPEBSRC 0x6101c
137 #define BCLRPAT_B 0x61020
138 #define VSYNCSHIFT_B 0x61028
140 #define HTOTAL_C 0x62000
141 #define HBLANK_C 0x62004
142 #define HSYNC_C 0x62008
143 #define VTOTAL_C 0x6200c
144 #define VBLANK_C 0x62010
145 #define VSYNC_C 0x62014
146 #define PIPECSRC 0x6201c
147 #define BCLRPAT_C 0x62020
148 #define VSYNCSHIFT_C 0x62028
150 #define PP_STATUS 0x61200
160 #define PP_SEQUENCE_NONE (0 << 28)
163 #define PP_SEQUENCE_MASK 0x30000000
166 #define PP_SEQUENCE_STATE_MASK 0x0000000f
168 #define PP_CONTROL 0x61204
169 #define POWER_TARGET_ON (1 << 0)
170 #define PANEL_UNLOCK_REGS (0xabcd << 16)
171 #define PANEL_UNLOCK_MASK (0xffff << 16)
175 #define PANEL_POWER_OFF (0 << 0)
176 #define PANEL_POWER_ON (1 << 0)
179 #define LVDSPP_ON 0x61208
180 #define LVDSPP_OFF 0x6120c
181 #define PP_CYCLE 0x61210
184 #define PP_ON_DELAYS 0x61208 /* Cedartrail */
186 #define PANEL_PORT_SELECT_LVDS (0 << 30)
188 #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
190 #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
191 #define PANEL_LIGHT_ON_DELAY_SHIFT 0
193 #define PP_OFF_DELAYS 0x6120c /* Cedartrail */
194 #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
196 #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
197 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0
199 #define PP_DIVISOR 0x61210 /* Cedartrail */
200 #define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
202 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
203 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0
205 #define PFIT_CONTROL 0x61230
211 #define VERT_INTERP_DISABLE (0 << 10)
215 #define HORIZ_INTERP_DISABLE (0 << 6)
221 #define PFIT_PGM_RATIOS 0x61234
222 #define PFIT_VERT_SCALE_MASK 0xfff00000
223 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
225 #define PFIT_AUTO_RATIOS 0x61238
227 #define DPLL_A 0x06014
228 #define DPLL_B 0x06018
236 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
238 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
240 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
241 #define DPLL_FPA0h1_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
248 # define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
253 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
258 #define PLL_REF_INPUT_DREFCLK (0 << 13)
271 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
279 #define SDVO_MULTIPLIER_MASK 0x000000ff
281 #define SDVO_MULTIPLIER_SHIFT_VGA 0
287 #define DPLL_A_MD 0x0601c
289 #define DPLL_B_MD 0x06020
295 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
298 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
317 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
324 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
325 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
327 #define DPLL_TEST 0x606c
328 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
337 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
339 #define ADPA 0x61100
341 #define ADPA_DAC_DISABLE 0
343 #define ADPA_PIPE_A_SELECT 0
346 #define ADPA_SETS_HVPOLARITY 0
348 #define ADPA_VSYNC_CNTL_ENABLE 0
350 #define ADPA_HSYNC_CNTL_ENABLE 0
352 #define ADPA_VSYNC_ACTIVE_LOW 0
354 #define ADPA_HSYNC_ACTIVE_LOW 0
356 #define FPA0 0x06040
357 #define FPA1 0x06044
358 #define FPB0 0x06048
359 #define FPB1 0x0604c
360 #define FP_N_DIV_MASK 0x003f0000
362 #define FP_M1_DIV_MASK 0x00003f00
364 #define FP_M2_DIV_MASK 0x0000003f
365 #define FP_M2_DIV_SHIFT 0
367 #define PORT_HOTPLUG_EN 0x61110
378 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
380 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
385 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
387 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
389 #define CRT_HOTPLUG_DETECT_MASK 0x000000F8
391 #define PORT_HOTPLUG_STAT 0x61114
397 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
401 #define SDVOB 0x61140
402 #define SDVOC 0x61160
436 #define LVDS 0x61180
453 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
461 #define LVDS_A3_POWER_DOWN (0 << 6)
468 #define LVDS_CLKB_POWER_DOWN (0 << 4)
476 #define LVDS_B0B3_POWER_DOWN (0 << 2)
479 #define PIPEACONF 0x70008
481 #define PIPEACONF_DISABLE 0
485 #define PIPEACONF_SINGLE_WIDE 0
486 #define PIPEACONF_PIPE_UNLOCKED 0
489 #define PIPEACONF_PALETTE 0
492 #define PIPECONF_PROGRESSIVE (0 << 21)
498 #define PIPEBCONF 0x71008
500 #define PIPEBCONF_DISABLE 0
502 #define PIPEBCONF_DISABLE 0
504 #define PIPEBCONF_PALETTE 0
506 #define PIPECCONF 0x72008
508 #define PIPEBGCMAXRED 0x71010
509 #define PIPEBGCMAXGREEN 0x71014
510 #define PIPEBGCMAXBLUE 0x71018
512 #define PIPEASTAT 0x70024
513 #define PIPEBSTAT 0x71024
514 #define PIPECSTAT 0x72024
538 #define HISTOGRAM_INT_CONTROL 0x61268
539 #define HISTOGRAM_BIN_DATA 0X61264
540 #define HISTOGRAM_LOGIC_CONTROL 0x61260
541 #define PWM_CONTROL_LOGIC 0x61250
548 #define PWM_PHASEIN_VB_COUNT 0x00001f00
549 #define PWM_PHASEIN_INC 0x0000001f
551 #define DPST_YUV_LUMA_MODE 0
553 #define PIPEAFRAMEHIGH 0x70040
554 #define PIPEAFRAMEPIXEL 0x70044
555 #define PIPEBFRAMEHIGH 0x71040
556 #define PIPEBFRAMEPIXEL 0x71044
557 #define PIPECFRAMEHIGH 0x72040
558 #define PIPECFRAMEPIXEL 0x72044
559 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
560 #define PIPE_FRAME_HIGH_SHIFT 0
561 #define PIPE_FRAME_LOW_MASK 0xff000000
563 #define PIPE_PIXEL_MASK 0x00ffffff
564 #define PIPE_PIXEL_SHIFT 0
566 #define FW_BLC_SELF 0x20e0
569 #define DSPARB 0x70030
570 #define DSPFW1 0x70034
571 #define DSP_FIFO_SR_WM_MASK 0xFF800000
573 #define CURSOR_B_FIFO_WM_MASK 0x003F0000
575 #define DSPFW2 0x70038
576 #define CURSOR_A_FIFO_WM_MASK 0x3F00
578 #define DSP_PLANE_C_FIFO_WM_MASK 0x7F
579 #define DSP_PLANE_C_FIFO_WM_SHIFT 0
580 #define DSPFW3 0x7003c
581 #define DSPFW4 0x70050
582 #define DSPFW5 0x70054
586 #define CURSOR_FIFO_SR_WM1_SHIFT 0
587 #define DSPFW6 0x70058
588 #define DSPCHICKENBIT 0x70400
589 #define DSPACNTR 0x70180
590 #define DSPBCNTR 0x71180
591 #define DSPCCNTR 0x72180
593 #define DISPLAY_PLANE_DISABLE 0
595 #define DISPPLANE_GAMMA_DISABLE 0
596 #define DISPPLANE_PIXFORMAT_MASK (0xf << 26)
597 #define DISPPLANE_8BPP (0x2 << 26)
598 #define DISPPLANE_15_16BPP (0x4 << 26)
599 #define DISPPLANE_16BPP (0x5 << 26)
600 #define DISPPLANE_32BPP_NO_ALPHA (0x6 << 26)
601 #define DISPPLANE_32BPP (0x7 << 26)
603 #define DISPPLANE_STEREO_DISABLE 0
606 #define DISPPLANE_SEL_PIPE_A 0
609 #define DISPPLANE_SRC_KEY_DISABLE 0
611 #define DISPPLANE_NO_LINE_DOUBLE 0
612 #define DISPPLANE_STEREO_POLARITY_FIRST 0
616 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
617 #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
621 #define DSPABASE 0x70184
622 #define DSPALINOFF 0x70184
623 #define DSPASTRIDE 0x70188
625 #define DSPBBASE 0x71184
626 #define DSPBLINOFF 0X71184
628 #define DSPBSTRIDE 0x71188
630 #define DSPCBASE 0x72184
631 #define DSPCLINOFF 0x72184
632 #define DSPCSTRIDE 0x72188
634 #define DSPAKEYVAL 0x70194
635 #define DSPAKEYMASK 0x70198
637 #define DSPAPOS 0x7018C /* reserved */
638 #define DSPASIZE 0x70190
639 #define DSPBPOS 0x7118C
640 #define DSPBSIZE 0x71190
641 #define DSPCPOS 0x7218C
642 #define DSPCSIZE 0x72190
644 #define DSPASURF 0x7019C
645 #define DSPATILEOFF 0x701A4
647 #define DSPBSURF 0x7119C
648 #define DSPBTILEOFF 0x711A4
650 #define DSPCSURF 0x7219C
651 #define DSPCTILEOFF 0x721A4
652 #define DSPCKEYMAXVAL 0x721A0
653 #define DSPCKEYMINVAL 0x72194
654 #define DSPCKEYMSK 0x72198
656 #define VGACNTRL 0x71400
664 #define OV_C_OFFSET 0x08000
665 #define OV_OVADD 0x30000
666 #define OV_DOVASTA 0x30008
669 # define OV_PIPE_A 0
671 #define OV_OGAMC5 0x30010
672 #define OV_OGAMC4 0x30014
673 #define OV_OGAMC3 0x30018
674 #define OV_OGAMC2 0x3001C
675 #define OV_OGAMC1 0x30020
676 #define OV_OGAMC0 0x30024
677 #define OVC_OVADD 0x38000
678 #define OVC_DOVCSTA 0x38008
679 #define OVC_OGAMC5 0x38010
680 #define OVC_OGAMC4 0x38014
681 #define OVC_OGAMC3 0x38018
682 #define OVC_OGAMC2 0x3801C
683 #define OVC_OGAMC1 0x38020
684 #define OVC_OGAMC0 0x38024
690 #define SWF0 0x71410
691 #define SWF1 0x71414
692 #define SWF2 0x71418
693 #define SWF3 0x7141c
694 #define SWF4 0x71420
695 #define SWF5 0x71424
696 #define SWF6 0x71428
701 #define SWF00 0x70410
702 #define SWF01 0x70414
703 #define SWF02 0x70418
704 #define SWF03 0x7041c
705 #define SWF04 0x70420
706 #define SWF05 0x70424
707 #define SWF06 0x70428
717 #define SWF30 0x72414
718 #define SWF31 0x72418
719 #define SWF32 0x7241c
725 #define PALETTE_A 0x0a000
726 #define PALETTE_B 0x0a800
727 #define PALETTE_C 0x0ac00
730 #define CURACNTR 0x70080
731 #define CURSOR_MODE_DISABLE 0x00
732 #define CURSOR_MODE_64_32B_AX 0x07
735 #define CURABASE 0x70084
736 #define CURAPOS 0x70088
737 #define CURSOR_POS_MASK 0x007FF
738 #define CURSOR_POS_SIGN 0x8000
739 #define CURSOR_X_SHIFT 0
741 #define CURBCNTR 0x700c0
742 #define CURBBASE 0x700c4
743 #define CURBPOS 0x700c8
744 #define CURCCNTR 0x700e0
745 #define CURCBASE 0x700e4
746 #define CURCPOS 0x700e8
751 #define IER 0x020a0
752 #define IIR 0x020a4
753 #define IMR 0x020a8
754 #define ISR 0x020ac
759 #define MRST_DPLL_A 0x0f014
761 #define MRST_FPA0 0x0f040
762 #define MRST_FPA1 0x0f044
763 #define MRST_PERF_MODE 0x020f4
768 #define HDMIPHYMISCCTL 0x61134
769 #define HDMI_PHY_POWER_DOWN 0x7f
770 #define HDMIB_CONTROL 0x61140
776 /* #define LVDS 0x61180 */
781 #define MIPI 0x61190
782 #define MIPI_C 0x62190
788 #define MIPIA_3LANE_MIPIC_1LANE 0x1
789 #define MIPIA_2LANE_MIPIC_2LANE 0x2
792 #define MIPI_TE_COUNT 0x61194
794 /* #define PP_CONTROL 0x61204 */
797 /* #define PFIT_CONTROL 0x61230 */
801 /* #define BLC_PWM_CTL 0x61254 */
803 #define MRST_BACKLIGHT_MODULATION_FREQ_MASK (0xffff << 16)
805 /* #define PIPEACONF 0x70008 */
807 /* #define DSPACNTR 0x70180 */
809 #define MRST_DSPABASE 0x7019c
810 #define MRST_DSPBBASE 0x7119c
819 #define MIPIC_REG_OFFSET 0x800
821 #define DEVICE_READY_REG 0xb000
823 #define EXIT_ULPS_DEV_READY 0x3
824 #define LP_OUTPUT_HOLD_RELEASE 0x810000
829 #define INTR_STAT_REG 0xb004
830 #define RX_SOT_ERROR (1 << 0)
857 #define INTR_EN_REG 0xb008
858 #define DSI_FUNC_PRG_REG 0xb00c
859 #define DPI_CHANNEL_NUMBER_POS 0x03
860 #define DBI_CHANNEL_NUMBER_POS 0x05
861 #define FMT_DPI_POS 0x07
862 #define FMT_DBI_POS 0x0A
863 #define DBI_DATA_WIDTH_POS 0x0D
866 #define RGB_565_FMT 0x01 /* RGB 565 FORMAT */
867 #define RGB_666_FMT 0x02 /* RGB 666 FORMAT */
868 #define LRGB_666_FMT 0x03 /* RGB LOOSELY PACKED
871 #define RGB_888_FMT 0x04 /* RGB 888 FORMAT */
872 #define VIRTUAL_CHANNEL_NUMBER_0 0x00 /* Virtual channel 0 */
873 #define VIRTUAL_CHANNEL_NUMBER_1 0x01 /* Virtual channel 1 */
874 #define VIRTUAL_CHANNEL_NUMBER_2 0x02 /* Virtual channel 2 */
875 #define VIRTUAL_CHANNEL_NUMBER_3 0x03 /* Virtual channel 3 */
877 #define DBI_NOT_SUPPORTED 0x00 /* command mode
880 #define DBI_DATA_WIDTH_16BIT 0x01 /* 16 bit data */
881 #define DBI_DATA_WIDTH_9BIT 0x02 /* 9 bit data */
882 #define DBI_DATA_WIDTH_8BIT 0x03 /* 8 bit data */
883 #define DBI_DATA_WIDTH_OPT1 0x04 /* option 1 */
884 #define DBI_DATA_WIDTH_OPT2 0x05 /* option 2 */
886 #define HS_TX_TIMEOUT_REG 0xb010
887 #define LP_RX_TIMEOUT_REG 0xb014
888 #define TURN_AROUND_TIMEOUT_REG 0xb018
889 #define DEVICE_RESET_REG 0xb01C
890 #define DPI_RESOLUTION_REG 0xb020
891 #define RES_V_POS 0x10
892 #define HORIZ_SYNC_PAD_COUNT_REG 0xb028
893 #define HORIZ_BACK_PORCH_COUNT_REG 0xb02C
894 #define HORIZ_FRONT_PORCH_COUNT_REG 0xb030
895 #define HORIZ_ACTIVE_AREA_COUNT_REG 0xb034
896 #define VERT_SYNC_PAD_COUNT_REG 0xb038
897 #define VERT_BACK_PORCH_COUNT_REG 0xb03c
898 #define VERT_FRONT_PORCH_COUNT_REG 0xb040
899 #define HIGH_LOW_SWITCH_COUNT_REG 0xb044
900 #define DPI_CONTROL_REG 0xb048
901 #define DPI_SHUT_DOWN (1 << 0)
908 #define DPI_DATA_REG 0xb04c
909 #define DPI_BACK_LIGHT_ON_DATA 0x07
910 #define DPI_BACK_LIGHT_OFF_DATA 0x17
911 #define INIT_COUNT_REG 0xb050
912 #define MAX_RET_PAK_REG 0xb054
913 #define VIDEO_FMT_REG 0xb058
915 #define EOT_DISABLE_REG 0xb05c
917 #define LP_BYTECLK_REG 0xb060
918 #define LP_GEN_DATA_REG 0xb064
919 #define HS_GEN_DATA_REG 0xb068
920 #define LP_GEN_CTRL_REG 0xb06C
921 #define HS_GEN_CTRL_REG 0xb070
922 #define DCS_CHANNEL_NUMBER_POS 0x6
923 #define MCS_COMMANDS_POS 0x8
924 #define WORD_COUNTS_POS 0x8
925 #define MCS_PARAMETER_POS 0x10
926 #define GEN_FIFO_STAT_REG 0xb074
927 #define HS_DATA_FIFO_FULL (1 << 0)
941 #define HS_LS_DBI_ENABLE_REG 0xb078
942 #define TXCLKESC_REG 0xb07c
943 #define DPHY_PARAM_REG 0xb080
944 #define DBI_BW_CTRL_REG 0xb084
945 #define CLK_LANE_SWT_REG 0xb088
950 #define MIPI_CONTROL_REG 0xb104
951 #define MIPI_2X_CLOCK_BITS ((1 << 0) | (1 << 1))
952 #define MIPI_DATA_ADDRESS_REG 0xb108
953 #define MIPI_DATA_LENGTH_REG 0xb10C
954 #define MIPI_COMMAND_ADDRESS_REG 0xb110
955 #define MIPI_COMMAND_LENGTH_REG 0xb114
956 #define MIPI_READ_DATA_RETURN_REG0 0xb118
957 #define MIPI_READ_DATA_RETURN_REG1 0xb11C
958 #define MIPI_READ_DATA_RETURN_REG2 0xb120
959 #define MIPI_READ_DATA_RETURN_REG3 0xb124
960 #define MIPI_READ_DATA_RETURN_REG4 0xb128
961 #define MIPI_READ_DATA_RETURN_REG5 0xb12C
962 #define MIPI_READ_DATA_RETURN_REG6 0xb130
963 #define MIPI_READ_DATA_RETURN_REG7 0xb134
964 #define MIPI_READ_DATA_VALID_REG 0xb138
967 #define soft_reset 0x01
972 #define get_power_mode 0x0a
976 #define get_address_mode 0x0b
980 #define get_pixel_format 0x0c
985 #define get_display_mode 0x0d
989 #define get_signal_mode 0x0e
993 #define get_diagnostic_result 0x0f
998 #define enter_sleep_mode 0x10
1005 #define exit_sleep_mode 0x11
1010 #define enter_partial_mode 0x12
1016 #define enter_normal_mode 0x13
1021 #define exit_invert_mode 0x20
1027 #define enter_invert_mode 0x21
1033 #define set_gamma_curve 0x26
1038 #define set_display_off 0x28
1044 #define set_display_on 0x29
1050 #define set_column_address 0x2a
1057 #define set_page_addr 0x2b
1064 #define write_mem_start 0x2c
1070 #define set_partial_area 0x30
1077 #define set_scroll_area 0x33
1081 #define set_tear_off 0x34
1086 #define set_tear_on 0x35
1091 #define set_address_mode 0x36
1095 * display modules frame memory to the display device, bits B[2:0] and B4.
1097 #define set_scroll_start 0x37
1106 #define exit_idle_mode 0x38
1110 #define enter_idle_mode 0x39
1117 #define set_pixel_format 0x3a
1122 * Bits D[2:0] DBI Pixel Format Definition
1125 #define DCS_PIXEL_FORMAT_3bpp 0x1
1126 #define DCS_PIXEL_FORMAT_8bpp 0x2
1127 #define DCS_PIXEL_FORMAT_12bpp 0x3
1128 #define DCS_PIXEL_FORMAT_16bpp 0x5
1129 #define DCS_PIXEL_FORMAT_18bpp 0x6
1130 #define DCS_PIXEL_FORMAT_24bpp 0x7
1132 #define write_mem_cont 0x3c
1140 #define set_tear_scanline 0x44
1145 #define get_scanline 0x45
1150 * the first line of V Sync and is denoted as Line 0.
1156 #define GEN_SHORT_WRITE_0 0x03 /* generic short write, no parameters */
1157 #define GEN_SHORT_WRITE_1 0x13 /* generic short write, 1 parameters */
1158 #define GEN_SHORT_WRITE_2 0x23 /* generic short write, 2 parameters */
1159 #define GEN_READ_0 0x04 /* generic read, no parameters */
1160 #define GEN_READ_1 0x14 /* generic read, 1 parameters */
1161 #define GEN_READ_2 0x24 /* generic read, 2 parameters */
1162 #define GEN_LONG_WRITE 0x29 /* generic long write */
1163 #define MCS_SHORT_WRITE_0 0x05 /* MCS short write, no parameters */
1164 #define MCS_SHORT_WRITE_1 0x15 /* MCS short write, 1 parameters */
1165 #define MCS_READ 0x06 /* MCS read, no parameters */
1166 #define MCS_LONG_WRITE 0x39 /* MCS long write */
1169 #define write_display_profile 0x50
1170 #define write_display_brightness 0x51
1171 #define write_ctrl_display 0x53
1172 #define write_ctrl_cabc 0x55
1173 #define UI_IMAGE 0x01
1174 #define STILL_IMAGE 0x02
1175 #define MOVING_IMAGE 0x03
1176 #define write_hysteresis 0x57
1177 #define write_gamma_setting 0x58
1178 #define write_cabc_min_bright 0x5e
1179 #define write_kbbc_profile 0x60
1181 #define tmd_write_display_brightness 0x8c
1192 #define GAMMA_AUTO (1 << 0)
1195 #define DCS_PIXEL_FORMAT_3BPP 0x1
1196 #define DCS_PIXEL_FORMAT_8BPP 0x2
1197 #define DCS_PIXEL_FORMAT_12BPP 0x3
1198 #define DCS_PIXEL_FORMAT_16BPP 0x5
1199 #define DCS_PIXEL_FORMAT_18BPP 0x6
1200 #define DCS_PIXEL_FORMAT_24BPP 0x7
1202 #define addr_mode_data 0xfc
1203 #define diag_res_data 0x00
1204 #define disp_mode_data 0x23
1205 #define pxl_fmt_data 0x77
1206 #define pwr_mode_data 0x74
1207 #define sig_mode_data 0x00
1209 #define scanline_data1 0xff
1210 #define scanline_data2 0xff
1211 #define NON_BURST_MODE_SYNC_PULSE 0x01 /* Non Burst Mode
1214 #define NON_BURST_MODE_SYNC_EVENTS 0x02 /* Non Burst Mode
1217 #define BURST_MODE 0x03 /* Burst Mode */
1218 #define DBI_COMMAND_BUFFER_SIZE 0x240 /* 0x32 */ /* 0x120 */
1220 * 0x100 Byte with 32
1223 #define DBI_DATA_BUFFER_SIZE 0x120 /* Allocate at least
1224 * 0x100 Byte with 32
1227 #define DBI_CB_TIME_OUT 0xFFFF
1231 #define SKU_83 0x01
1232 #define SKU_100 0x02
1233 #define SKU_100L 0x04
1234 #define SKU_BYPASS 0x08
1245 #define SB_PCKT 0x02100 /* cedarview */
1248 # define SB_OPCODE_READ 0
1252 # define SB_DEST_DPLL 0x88
1255 # define SB_BUSY (1 << 0)
1257 #define DSPCLK_GATE_D 0x6200
1266 #define RAMCLK_GATE_D 0x6210
1269 #define SB_DATA 0x02104 /* cedarview */
1271 #define SB_ADDR 0x02108 /* cedarview */
1272 #define DPIO_CFG 0x02110 /* cedarview */
1277 # define DPIO_CMN_RESET_N (1 << 0)
1280 #define _SB_M_A 0x8008
1281 #define _SB_M_B 0x8028
1283 # define SB_M_DIVIDER_MASK (0xFF << 24)
1286 #define _SB_N_VCO_A 0x8014
1287 #define _SB_N_VCO_B 0x8034
1297 #define SB_REF_DPLLA 0x8010
1298 #define SB_REF_DPLLB 0x8030
1299 #define REF_CLK_MASK (0x3 << 13)
1300 #define REF_CLK_CORE (0 << 13)
1305 #define _SB_REF_A 0x8018
1306 #define _SB_REF_B 0x8038
1309 #define _SB_P_A 0x801c
1310 #define _SB_P_B 0x803c
1314 #define SB_P2_10 0 /* HDMI, DP, DAC */
1321 #define PSB_LANE0 0x120
1322 #define PSB_LANE1 0x220
1323 #define PSB_LANE2 0x2320
1324 #define PSB_LANE3 0x2420
1326 #define LANE_PLL_MASK (0x7 << 20)
1327 #define LANE_PLL_ENABLE (0x3 << 20)
1328 #define LANE_PLL_PIPE(p) (((p) == 0) ? (1 << 21) : (0 << 21))
1330 #define DP_B 0x64100
1331 #define DP_C 0x64200
1338 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
1346 #define DP_VOLTAGE_0_4 (0 << 25)
1356 #define DP_PRE_EMPHASIS_0 (0 << 22)
1364 #define DP_PORT_WIDTH_1 (0 << 19)
1399 #define DPB_AUX_CH_CTL 0x64110
1400 #define DPB_AUX_CH_DATA1 0x64114
1401 #define DPB_AUX_CH_DATA2 0x64118
1402 #define DPB_AUX_CH_DATA3 0x6411c
1403 #define DPB_AUX_CH_DATA4 0x64120
1404 #define DPB_AUX_CH_DATA5 0x64124
1406 #define DPC_AUX_CH_CTL 0x64210
1407 #define DPC_AUX_CH_DATA1 0x64214
1408 #define DPC_AUX_CH_DATA2 0x64218
1409 #define DPC_AUX_CH_DATA3 0x6421c
1410 #define DPC_AUX_CH_DATA4 0x64220
1411 #define DPC_AUX_CH_DATA5 0x64224
1417 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
1423 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
1425 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
1432 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
1433 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
1449 #define _PIPEA_GMCH_DATA_M 0x70050
1450 #define _PIPEB_GMCH_DATA_M 0x71050
1452 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
1453 #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
1456 #define PIPE_GMCH_DATA_M_MASK (0xffffff)
1458 #define _PIPEA_GMCH_DATA_N 0x70054
1459 #define _PIPEB_GMCH_DATA_N 0x71054
1460 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
1473 #define _PIPEA_DP_LINK_M 0x70060
1474 #define _PIPEB_DP_LINK_M 0x71060
1475 #define PIPEA_DP_LINK_M_MASK (0xffffff)
1477 #define _PIPEA_DP_LINK_N 0x70064
1478 #define _PIPEB_DP_LINK_N 0x71064
1479 #define PIPEA_DP_LINK_N_MASK (0xffffff)
1487 #define PIPE_8BPC (0 << 5)