322 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_max_lane_count()  local
325 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {  in cdv_intel_dp_max_lane_count()
326 		max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;  in cdv_intel_dp_max_lane_count()
340 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_max_link_bw()  local
341 	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];  in cdv_intel_dp_max_link_bw()
378 	struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;  in cdv_intel_edp_panel_vdd_on()  local
381 	if (intel_dp->panel_on) {  in cdv_intel_edp_panel_vdd_on()
392 	msleep(intel_dp->panel_power_up_delay);  in cdv_intel_edp_panel_vdd_on()
413 	struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;  in cdv_intel_edp_panel_on()  local
416 	if (intel_dp->panel_on)  in cdv_intel_edp_panel_on()
429 		intel_dp->panel_on = false;  in cdv_intel_edp_panel_on()
431 		intel_dp->panel_on = true;  in cdv_intel_edp_panel_on()
432 	msleep(intel_dp->panel_power_up_delay);  in cdv_intel_edp_panel_on()
441 	struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;  in cdv_intel_edp_panel_off()  local
450 	intel_dp->panel_on = false;  in cdv_intel_edp_panel_off()
465 	msleep(intel_dp->panel_power_cycle_delay);  in cdv_intel_edp_panel_off()
492 	struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;  in cdv_intel_edp_backlight_off()  local
502 	msleep(intel_dp->backlight_off_delay);  in cdv_intel_edp_backlight_off()
510 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_mode_valid()  local
515 	if (is_edp(encoder) && intel_dp->panel_fixed_mode) {  in cdv_intel_dp_mode_valid()
516 		if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)  in cdv_intel_dp_mode_valid()
518 		if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)  in cdv_intel_dp_mode_valid()
569 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_aux_ch()  local
570 	uint32_t output_reg = intel_dp->output_reg;  in cdv_intel_dp_aux_ch()
750 	struct cdv_intel_dp *intel_dp = container_of(adapter,  in cdv_intel_dp_i2c_aux_ch()  local
753 	struct gma_encoder *encoder = intel_dp->encoder;  in cdv_intel_dp_i2c_aux_ch()
846 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_i2c_init()  local
851 	intel_dp->algo.running = false;  in cdv_intel_dp_i2c_init()
852 	intel_dp->algo.address = 0;  in cdv_intel_dp_i2c_init()
853 	intel_dp->algo.aux_ch = cdv_intel_dp_i2c_aux_ch;  in cdv_intel_dp_i2c_init()
855 	memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));  in cdv_intel_dp_i2c_init()
856 	intel_dp->adapter.owner = THIS_MODULE;  in cdv_intel_dp_i2c_init()
857 	intel_dp->adapter.class = I2C_CLASS_DDC;  in cdv_intel_dp_i2c_init()
858 	strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);  in cdv_intel_dp_i2c_init()
859 	intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';  in cdv_intel_dp_i2c_init()
860 	intel_dp->adapter.algo_data = &intel_dp->algo;  in cdv_intel_dp_i2c_init()
861 	intel_dp->adapter.dev.parent = connector->base.kdev;  in cdv_intel_dp_i2c_init()
865 	ret = i2c_dp_aux_add_bus(&intel_dp->adapter);  in cdv_intel_dp_i2c_init()
896 	struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;  in cdv_intel_dp_mode_fixup()  local
904 	if (is_edp(intel_encoder) && intel_dp->panel_fixed_mode) {  in cdv_intel_dp_mode_fixup()
905 		cdv_intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);  in cdv_intel_dp_mode_fixup()
906 		refclock = intel_dp->panel_fixed_mode->clock;  in cdv_intel_dp_mode_fixup()
915 				intel_dp->link_bw = bws[clock];  in cdv_intel_dp_mode_fixup()
916 				intel_dp->lane_count = lane_count;  in cdv_intel_dp_mode_fixup()
917 				adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw);  in cdv_intel_dp_mode_fixup()
920 				       intel_dp->link_bw, intel_dp->lane_count,  in cdv_intel_dp_mode_fixup()
928 		intel_dp->lane_count = max_lane_count;  in cdv_intel_dp_mode_fixup()
929 		intel_dp->link_bw = bws[max_clock];  in cdv_intel_dp_mode_fixup()
930 		adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw);  in cdv_intel_dp_mode_fixup()
933 			      intel_dp->link_bw, intel_dp->lane_count,  in cdv_intel_dp_mode_fixup()
999 		struct cdv_intel_dp *intel_dp;  in cdv_intel_dp_set_m_n()  local
1005 		intel_dp = intel_encoder->dev_priv;  in cdv_intel_dp_set_m_n()
1007 			lane_count = intel_dp->lane_count;  in cdv_intel_dp_set_m_n()
1010 			lane_count = intel_dp->lane_count;  in cdv_intel_dp_set_m_n()
1041 	struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;  in cdv_intel_dp_mode_set()  local
1044 	intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;  in cdv_intel_dp_mode_set()
1045 	intel_dp->DP |= intel_dp->color_range;  in cdv_intel_dp_mode_set()
1048 		intel_dp->DP |= DP_SYNC_HS_HIGH;  in cdv_intel_dp_mode_set()
1050 		intel_dp->DP |= DP_SYNC_VS_HIGH;  in cdv_intel_dp_mode_set()
1052 	intel_dp->DP |= DP_LINK_TRAIN_OFF;  in cdv_intel_dp_mode_set()
1054 	switch (intel_dp->lane_count) {  in cdv_intel_dp_mode_set()
1056 		intel_dp->DP |= DP_PORT_WIDTH_1;  in cdv_intel_dp_mode_set()
1059 		intel_dp->DP |= DP_PORT_WIDTH_2;  in cdv_intel_dp_mode_set()
1062 		intel_dp->DP |= DP_PORT_WIDTH_4;  in cdv_intel_dp_mode_set()
1065 	if (intel_dp->has_audio)  in cdv_intel_dp_mode_set()
1066 		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;  in cdv_intel_dp_mode_set()
1068 	memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);  in cdv_intel_dp_mode_set()
1069 	intel_dp->link_configuration[0] = intel_dp->link_bw;  in cdv_intel_dp_mode_set()
1070 	intel_dp->link_configuration[1] = intel_dp->lane_count;  in cdv_intel_dp_mode_set()
1075 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&  in cdv_intel_dp_mode_set()
1076 	    (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {  in cdv_intel_dp_mode_set()
1077 		intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;  in cdv_intel_dp_mode_set()
1078 		intel_dp->DP |= DP_ENHANCED_FRAMING;  in cdv_intel_dp_mode_set()
1083 		intel_dp->DP |= DP_PIPEB_SELECT;  in cdv_intel_dp_mode_set()
1085 	REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN));  in cdv_intel_dp_mode_set()
1086 	DRM_DEBUG_KMS("DP expected reg is %x\n", intel_dp->DP);  in cdv_intel_dp_mode_set()
1107 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_sink_dpms()  local
1111 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)  in cdv_intel_dp_sink_dpms()
1169 	struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;  in cdv_intel_dp_dpms()  local
1171 	uint32_t dp_reg = REG_READ(intel_dp->output_reg);  in cdv_intel_dp_dpms()
1230 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_get_link_status()  local
1233 					      intel_dp->link_status,  in cdv_intel_dp_get_link_status()
1275 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_get_adjust_train()  local
1280 	for (lane = 0; lane < intel_dp->lane_count; lane++) {  in cdv_intel_get_adjust_train()
1281 		uint8_t this_v = cdv_intel_get_adjust_request_voltage(intel_dp->link_status, lane);  in cdv_intel_get_adjust_train()
1282 		uint8_t this_p = cdv_intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);  in cdv_intel_get_adjust_train()
1297 		intel_dp->train_set[lane] = v | p;  in cdv_intel_get_adjust_train()
1334 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_channel_eq_ok()  local
1339 	lane_align = cdv_intel_dp_link_status(intel_dp->link_status,  in cdv_intel_channel_eq_ok()
1343 	for (lane = 0; lane < intel_dp->lane_count; lane++) {  in cdv_intel_channel_eq_ok()
1344 		lane_status = cdv_intel_get_lane_status(intel_dp->link_status, lane);  in cdv_intel_channel_eq_ok()
1358 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_set_link_train()  local
1360 	REG_WRITE(intel_dp->output_reg, dp_reg_value);  in cdv_intel_dp_set_link_train()
1361 	REG_READ(intel_dp->output_reg);  in cdv_intel_dp_set_link_train()
1382 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dplink_set_level()  local
1386 					intel_dp->train_set,  in cdv_intel_dplink_set_level()
1387 					intel_dp->lane_count);  in cdv_intel_dplink_set_level()
1389 	if (ret != intel_dp->lane_count) {  in cdv_intel_dplink_set_level()
1391 				intel_dp->train_set[0], intel_dp->lane_count);  in cdv_intel_dplink_set_level()
1401 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_set_vswing_premph()  local
1405 	if (intel_dp->output_reg == DP_B)  in cdv_intel_dp_set_vswing_premph()
1467 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_start_link_train()  local
1473 	uint32_t DP = intel_dp->DP;  in cdv_intel_dp_start_link_train()
1481 	REG_WRITE(intel_dp->output_reg, reg);  in cdv_intel_dp_start_link_train()
1482 	REG_READ(intel_dp->output_reg);  in cdv_intel_dp_start_link_train()
1488 				  intel_dp->link_configuration,  in cdv_intel_dp_start_link_train()
1491 	memset(intel_dp->train_set, 0, 4);  in cdv_intel_dp_start_link_train()
1502 				intel_dp->train_set[0],  in cdv_intel_dp_start_link_train()
1503 				intel_dp->link_configuration[0],  in cdv_intel_dp_start_link_train()
1504 				intel_dp->link_configuration[1]);  in cdv_intel_dp_start_link_train()
1509 		cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]);  in cdv_intel_dp_start_link_train()
1519 				intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2],  in cdv_intel_dp_start_link_train()
1520 				intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]);  in cdv_intel_dp_start_link_train()
1522 		if (cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {  in cdv_intel_dp_start_link_train()
1529 		for (i = 0; i < intel_dp->lane_count; i++)  in cdv_intel_dp_start_link_train()
1530 			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)  in cdv_intel_dp_start_link_train()
1532 		if (i == intel_dp->lane_count)  in cdv_intel_dp_start_link_train()
1536 		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {  in cdv_intel_dp_start_link_train()
1542 		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;  in cdv_intel_dp_start_link_train()
1550 		DRM_DEBUG_KMS("failure in DP patter 1 training, train set %x\n", intel_dp->train_set[0]);  in cdv_intel_dp_start_link_train()
1553 	intel_dp->DP = DP;  in cdv_intel_dp_start_link_train()
1560 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_complete_link_train()  local
1563 	uint32_t DP = intel_dp->DP;  in cdv_intel_dp_complete_link_train()
1575 				intel_dp->train_set[0],  in cdv_intel_dp_complete_link_train()
1576 				intel_dp->link_configuration[0],  in cdv_intel_dp_complete_link_train()
1577 				intel_dp->link_configuration[1]);  in cdv_intel_dp_complete_link_train()
1592 		cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]);  in cdv_intel_dp_complete_link_train()
1601 				intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2],  in cdv_intel_dp_complete_link_train()
1602 				intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]);  in cdv_intel_dp_complete_link_train()
1605 		if (!cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {  in cdv_intel_dp_complete_link_train()
1633 	REG_WRITE(intel_dp->output_reg, reg);  in cdv_intel_dp_complete_link_train()
1634 	REG_READ(intel_dp->output_reg);  in cdv_intel_dp_complete_link_train()
1643 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_link_down()  local
1644 	uint32_t DP = intel_dp->DP;  in cdv_intel_dp_link_down()
1646 	if ((REG_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)  in cdv_intel_dp_link_down()
1654 		REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);  in cdv_intel_dp_link_down()
1656 	REG_READ(intel_dp->output_reg);  in cdv_intel_dp_link_down()
1660 	REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);  in cdv_intel_dp_link_down()
1661 	REG_READ(intel_dp->output_reg);  in cdv_intel_dp_link_down()
1666 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_dp_detect()  local
1670 	if (cdv_intel_dp_aux_native_read(encoder, 0x000, intel_dp->dpcd,  in cdv_dp_detect()
1671 				     sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))  in cdv_dp_detect()
1673 		if (intel_dp->dpcd[DP_DPCD_REV] != 0)  in cdv_dp_detect()
1678 			intel_dp->dpcd[0], intel_dp->dpcd[1],  in cdv_dp_detect()
1679 			intel_dp->dpcd[2], intel_dp->dpcd[3]);  in cdv_dp_detect()
1693 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_detect()  local
1698 	intel_dp->has_audio = false;  in cdv_intel_dp_detect()
1709 	if (intel_dp->force_audio) {  in cdv_intel_dp_detect()
1710 		intel_dp->has_audio = intel_dp->force_audio > 0;  in cdv_intel_dp_detect()
1712 		edid = drm_get_edid(connector, &intel_dp->adapter);  in cdv_intel_dp_detect()
1714 			intel_dp->has_audio = drm_detect_monitor_audio(edid);  in cdv_intel_dp_detect()
1727 	struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;  in cdv_intel_dp_get_modes()  local
1733 	edid = drm_get_edid(connector, &intel_dp->adapter);  in cdv_intel_dp_get_modes()
1746 			if (edp && !intel_dp->panel_fixed_mode) {  in cdv_intel_dp_get_modes()
1751 						intel_dp->panel_fixed_mode =  in cdv_intel_dp_get_modes()
1760 		if (!intel_dp->panel_fixed_mode && dev_priv->lfp_lvds_vbt_mode) {  in cdv_intel_dp_get_modes()
1761 			intel_dp->panel_fixed_mode =  in cdv_intel_dp_get_modes()
1763 			if (intel_dp->panel_fixed_mode) {  in cdv_intel_dp_get_modes()
1764 				intel_dp->panel_fixed_mode->type |=  in cdv_intel_dp_get_modes()
1768 		if (intel_dp->panel_fixed_mode != NULL) {  in cdv_intel_dp_get_modes()
1770 			mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);  in cdv_intel_dp_get_modes()
1783 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_detect_audio()  local
1791 	edid = drm_get_edid(connector, &intel_dp->adapter);  in cdv_intel_dp_detect_audio()
1809 	struct cdv_intel_dp *intel_dp = encoder->dev_priv;  in cdv_intel_dp_set_property()  local
1820 		if (i == intel_dp->force_audio)  in cdv_intel_dp_set_property()
1823 		intel_dp->force_audio = i;  in cdv_intel_dp_set_property()
1830 		if (has_audio == intel_dp->has_audio)  in cdv_intel_dp_set_property()
1833 		intel_dp->has_audio = has_audio;  in cdv_intel_dp_set_property()
1838 		if (val == !!intel_dp->color_range)  in cdv_intel_dp_set_property()
1841 		intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;  in cdv_intel_dp_set_property()
1863 	struct cdv_intel_dp *intel_dp = gma_encoder->dev_priv;  in cdv_intel_dp_destroy()  local
1867 		kfree(intel_dp->panel_fixed_mode);  in cdv_intel_dp_destroy()
1868 		intel_dp->panel_fixed_mode = NULL;  in cdv_intel_dp_destroy()
1870 	i2c_del_adapter(&intel_dp->adapter);  in cdv_intel_dp_destroy()
1952 	struct cdv_intel_dp *intel_dp;  in cdv_intel_dp_init()  local
1962 	intel_dp = kzalloc(sizeof(struct cdv_intel_dp), GFP_KERNEL);  in cdv_intel_dp_init()
1963 	if (!intel_dp)  in cdv_intel_dp_init()
1983 	gma_encoder->dev_priv=intel_dp;  in cdv_intel_dp_init()
1984 	intel_dp->encoder = gma_encoder;  in cdv_intel_dp_init()
1985 	intel_dp->output_reg = output_reg;  in cdv_intel_dp_init()
2052 		intel_dp->panel_power_up_delay = cur.t1_t3 / 10;  in cdv_intel_dp_init()
2053                 intel_dp->backlight_on_delay = cur.t8 / 10;  in cdv_intel_dp_init()
2054                 intel_dp->backlight_off_delay = cur.t9 / 10;  in cdv_intel_dp_init()
2055                 intel_dp->panel_power_down_delay = cur.t10 / 10;  in cdv_intel_dp_init()
2056                 intel_dp->panel_power_cycle_delay = (cur.t11_t12 - 1) * 100;  in cdv_intel_dp_init()
2059                               intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,  in cdv_intel_dp_init()
2060                               intel_dp->panel_power_cycle_delay);  in cdv_intel_dp_init()
2063                               intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);  in cdv_intel_dp_init()
2068 					       intel_dp->dpcd,  in cdv_intel_dp_init()
2069 					       sizeof(intel_dp->dpcd));  in cdv_intel_dp_init()
2079 				intel_dp->dpcd[0], intel_dp->dpcd[1],  in cdv_intel_dp_init()
2080 				intel_dp->dpcd[2], intel_dp->dpcd[3]);  in cdv_intel_dp_init()