Lines Matching +full:exynos4210 +full:- +full:fimd
1 // SPDX-License-Identifier: GPL-2.0-or-later
36 * FIMD stands for Fully Interactive Mobile Display and
64 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
66 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
91 /* FIMD has totally five hardware windows. */
203 { .compatible = "samsung,s3c6400-fimd",
205 { .compatible = "samsung,s5pv210-fimd",
207 { .compatible = "samsung,exynos3250-fimd",
209 { .compatible = "samsung,exynos4210-fimd",
211 { .compatible = "samsung,exynos5250-fimd",
213 { .compatible = "samsung,exynos5420-fimd",
258 val = (val & mask) | (readl(ctx->regs + reg) & ~mask); in fimd_set_bits()
259 writel(val, ctx->regs + reg); in fimd_set_bits()
264 struct fimd_context *ctx = crtc->ctx; in fimd_enable_vblank()
267 if (ctx->suspended) in fimd_enable_vblank()
268 return -EPERM; in fimd_enable_vblank()
270 if (!test_and_set_bit(0, &ctx->irq_flags)) { in fimd_enable_vblank()
271 val = readl(ctx->regs + VIDINTCON0); in fimd_enable_vblank()
275 if (ctx->i80_if) { in fimd_enable_vblank()
288 writel(val, ctx->regs + VIDINTCON0); in fimd_enable_vblank()
296 struct fimd_context *ctx = crtc->ctx; in fimd_disable_vblank()
299 if (ctx->suspended) in fimd_disable_vblank()
302 if (test_and_clear_bit(0, &ctx->irq_flags)) { in fimd_disable_vblank()
303 val = readl(ctx->regs + VIDINTCON0); in fimd_disable_vblank()
307 if (ctx->i80_if) { in fimd_disable_vblank()
314 writel(val, ctx->regs + VIDINTCON0); in fimd_disable_vblank()
320 struct fimd_context *ctx = crtc->ctx; in fimd_wait_for_vblank()
322 if (ctx->suspended) in fimd_wait_for_vblank()
325 atomic_set(&ctx->wait_vsync_event, 1); in fimd_wait_for_vblank()
328 * wait for FIMD to signal VSYNC interrupt or return after in fimd_wait_for_vblank()
331 if (!wait_event_timeout(ctx->wait_vsync_queue, in fimd_wait_for_vblank()
332 !atomic_read(&ctx->wait_vsync_event), in fimd_wait_for_vblank()
334 DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n"); in fimd_wait_for_vblank()
340 u32 val = readl(ctx->regs + WINCON(win)); in fimd_enable_video_output()
347 writel(val, ctx->regs + WINCON(win)); in fimd_enable_video_output()
354 u32 val = readl(ctx->regs + SHADOWCON); in fimd_enable_shadow_channel_path()
361 writel(val, ctx->regs + SHADOWCON); in fimd_enable_shadow_channel_path()
366 struct fimd_context *ctx = crtc->ctx; in fimd_clear_channels()
371 ret = pm_runtime_resume_and_get(ctx->dev); in fimd_clear_channels()
373 dev_err(ctx->dev, "failed to enable FIMD device.\n"); in fimd_clear_channels()
377 clk_prepare_enable(ctx->bus_clk); in fimd_clear_channels()
378 clk_prepare_enable(ctx->lcd_clk); in fimd_clear_channels()
382 u32 val = readl(ctx->regs + WINCON(win)); in fimd_clear_channels()
387 if (ctx->driver_data->has_shadowcon) in fimd_clear_channels()
397 ctx->suspended = false; in fimd_clear_channels()
399 fimd_enable_vblank(ctx->crtc); in fimd_clear_channels()
400 fimd_wait_for_vblank(ctx->crtc); in fimd_clear_channels()
401 fimd_disable_vblank(ctx->crtc); in fimd_clear_channels()
403 ctx->suspended = true; in fimd_clear_channels()
406 clk_disable_unprepare(ctx->lcd_clk); in fimd_clear_channels()
407 clk_disable_unprepare(ctx->bus_clk); in fimd_clear_channels()
409 pm_runtime_put(ctx->dev); in fimd_clear_channels()
418 struct drm_display_mode *mode = &state->adjusted_mode; in fimd_atomic_check()
419 struct fimd_context *ctx = crtc->ctx; in fimd_atomic_check()
423 if (mode->clock == 0) { in fimd_atomic_check()
424 DRM_DEV_ERROR(ctx->dev, "Mode has zero clock value.\n"); in fimd_atomic_check()
425 return -EINVAL; in fimd_atomic_check()
428 ideal_clk = mode->clock * 1000; in fimd_atomic_check()
430 if (ctx->i80_if) { in fimd_atomic_check()
438 lcd_rate = clk_get_rate(ctx->lcd_clk); in fimd_atomic_check()
440 DRM_DEV_ERROR(ctx->dev, in fimd_atomic_check()
443 return -EINVAL; in fimd_atomic_check()
449 DRM_DEV_ERROR(ctx->dev, "requested pixel clock(%lu) too low\n", in fimd_atomic_check()
451 return -EINVAL; in fimd_atomic_check()
454 ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff; in fimd_atomic_check()
461 void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base; in fimd_setup_trigger()
462 u32 trg_type = ctx->driver_data->trg_type; in fimd_setup_trigger()
468 if (ctx->driver_data->has_hw_trigger) in fimd_setup_trigger()
470 if (ctx->driver_data->has_trigger_per_te) in fimd_setup_trigger()
481 struct fimd_context *ctx = crtc->ctx; in fimd_commit()
482 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; in fimd_commit()
483 const struct fimd_driver_data *driver_data = ctx->driver_data; in fimd_commit()
484 void *timing_base = ctx->regs + driver_data->timing_base; in fimd_commit()
487 if (ctx->suspended) in fimd_commit()
491 if (mode->htotal == 0 || mode->vtotal == 0) in fimd_commit()
494 if (ctx->i80_if) { in fimd_commit()
495 val = ctx->i80ifcon | I80IFEN_ENABLE; in fimd_commit()
502 if (driver_data->has_vtsel && ctx->sysreg && in fimd_commit()
503 regmap_update_bits(ctx->sysreg, in fimd_commit()
504 driver_data->lcdblk_offset, in fimd_commit()
505 0x3 << driver_data->lcdblk_vt_shift, in fimd_commit()
506 0x1 << driver_data->lcdblk_vt_shift)) { in fimd_commit()
507 DRM_DEV_ERROR(ctx->dev, in fimd_commit()
516 vidcon1 = ctx->vidcon1; in fimd_commit()
517 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in fimd_commit()
519 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in fimd_commit()
521 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); in fimd_commit()
524 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; in fimd_commit()
525 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; in fimd_commit()
526 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; in fimd_commit()
528 val = VIDTCON0_VBPD(vbpd - 1) | in fimd_commit()
529 VIDTCON0_VFPD(vfpd - 1) | in fimd_commit()
530 VIDTCON0_VSPW(vsync_len - 1); in fimd_commit()
531 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); in fimd_commit()
534 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; in fimd_commit()
535 hbpd = mode->crtc_htotal - mode->crtc_hsync_end; in fimd_commit()
536 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; in fimd_commit()
538 val = VIDTCON1_HBPD(hbpd - 1) | in fimd_commit()
539 VIDTCON1_HFPD(hfpd - 1) | in fimd_commit()
540 VIDTCON1_HSPW(hsync_len - 1); in fimd_commit()
541 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); in fimd_commit()
544 if (driver_data->has_vidoutcon) in fimd_commit()
545 writel(ctx->vidout_con, timing_base + VIDOUT_CON); in fimd_commit()
548 if (ctx->sysreg && regmap_update_bits(ctx->sysreg, in fimd_commit()
549 driver_data->lcdblk_offset, in fimd_commit()
550 0x1 << driver_data->lcdblk_bypass_shift, in fimd_commit()
551 0x1 << driver_data->lcdblk_bypass_shift)) { in fimd_commit()
552 DRM_DEV_ERROR(ctx->dev, in fimd_commit()
560 if (driver_data->has_mic_bypass && ctx->sysreg && in fimd_commit()
561 regmap_update_bits(ctx->sysreg, in fimd_commit()
562 driver_data->lcdblk_offset, in fimd_commit()
563 0x1 << driver_data->lcdblk_mic_bypass_shift, in fimd_commit()
564 0x1 << driver_data->lcdblk_mic_bypass_shift)) { in fimd_commit()
565 DRM_DEV_ERROR(ctx->dev, in fimd_commit()
571 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | in fimd_commit()
572 VIDTCON2_HOZVAL(mode->hdisplay - 1) | in fimd_commit()
573 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) | in fimd_commit()
574 VIDTCON2_HOZVAL_E(mode->hdisplay - 1); in fimd_commit()
575 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); in fimd_commit()
583 val = ctx->vidcon0; in fimd_commit()
586 if (ctx->driver_data->has_clksel) in fimd_commit()
589 if (ctx->clkdiv > 1) in fimd_commit()
590 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR; in fimd_commit()
592 writel(val, ctx->regs + VIDCON0); in fimd_commit()
648 writel(val, ctx->regs + VIDOSD_C(win)); in fimd_win_set_bldmod()
652 writel(val, ctx->regs + VIDWnALPHA0(win)); in fimd_win_set_bldmod()
656 writel(val, ctx->regs + VIDWnALPHA1(win)); in fimd_win_set_bldmod()
665 struct exynos_drm_plane plane = ctx->planes[win]; in fimd_win_set_pixfmt()
668 uint32_t pixel_format = fb->format->format; in fimd_win_set_pixfmt()
669 unsigned int alpha = state->base.alpha; in fimd_win_set_pixfmt()
673 if (fb->format->has_alpha) in fimd_win_set_pixfmt()
674 pixel_alpha = state->base.pixel_blend_mode; in fimd_win_set_pixfmt()
682 if (ctx->driver_data->has_limited_fmt && !win) { in fimd_win_set_pixfmt()
725 writel(WIN_RGB_ORDER_REVERSE, ctx->regs + WIN_RGB_ORDER(win)); in fimd_win_set_pixfmt()
728 writel(WIN_RGB_ORDER_FORWARD, ctx->regs + WIN_RGB_ORDER(win)); in fimd_win_set_pixfmt()
733 * Setting dma-burst to 16Word causes permanent tearing for very small in fimd_win_set_pixfmt()
737 * still better to change dma-burst than displaying garbage. in fimd_win_set_pixfmt()
762 writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); in fimd_win_set_colkey()
763 writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); in fimd_win_set_colkey()
767 * fimd_shadow_protect_win() - disable updating values from shadow registers at vsync
782 * if the dma is started then fimd hardware could malfunction so in fimd_shadow_protect_win()
788 if (ctx->driver_data->has_shadowcon) { in fimd_shadow_protect_win()
796 val = readl(ctx->regs + reg); in fimd_shadow_protect_win()
801 writel(val, ctx->regs + reg); in fimd_shadow_protect_win()
806 struct fimd_context *ctx = crtc->ctx; in fimd_atomic_begin()
809 if (ctx->suspended) in fimd_atomic_begin()
818 struct fimd_context *ctx = crtc->ctx; in fimd_atomic_flush()
821 if (ctx->suspended) in fimd_atomic_flush()
834 to_exynos_plane_state(plane->base.state); in fimd_update_plane()
835 struct fimd_context *ctx = crtc->ctx; in fimd_update_plane()
836 struct drm_framebuffer *fb = state->base.fb; in fimd_update_plane()
840 unsigned int win = plane->index; in fimd_update_plane()
841 unsigned int cpp = fb->format->cpp[0]; in fimd_update_plane()
842 unsigned int pitch = fb->pitches[0]; in fimd_update_plane()
844 if (ctx->suspended) in fimd_update_plane()
847 offset = state->src.x * cpp; in fimd_update_plane()
848 offset += state->src.y * pitch; in fimd_update_plane()
853 writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); in fimd_update_plane()
856 size = pitch * state->crtc.h; in fimd_update_plane()
858 writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); in fimd_update_plane()
860 DRM_DEV_DEBUG_KMS(ctx->dev, in fimd_update_plane()
863 DRM_DEV_DEBUG_KMS(ctx->dev, "ovl_width = %d, ovl_height = %d\n", in fimd_update_plane()
864 state->crtc.w, state->crtc.h); in fimd_update_plane()
867 buf_offsize = pitch - (state->crtc.w * cpp); in fimd_update_plane()
868 line_size = state->crtc.w * cpp; in fimd_update_plane()
873 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); in fimd_update_plane()
876 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) | in fimd_update_plane()
877 VIDOSDxA_TOPLEFT_Y(state->crtc.y) | in fimd_update_plane()
878 VIDOSDxA_TOPLEFT_X_E(state->crtc.x) | in fimd_update_plane()
879 VIDOSDxA_TOPLEFT_Y_E(state->crtc.y); in fimd_update_plane()
880 writel(val, ctx->regs + VIDOSD_A(win)); in fimd_update_plane()
882 last_x = state->crtc.x + state->crtc.w; in fimd_update_plane()
884 last_x--; in fimd_update_plane()
885 last_y = state->crtc.y + state->crtc.h; in fimd_update_plane()
887 last_y--; in fimd_update_plane()
892 writel(val, ctx->regs + VIDOSD_B(win)); in fimd_update_plane()
894 DRM_DEV_DEBUG_KMS(ctx->dev, in fimd_update_plane()
896 state->crtc.x, state->crtc.y, last_x, last_y); in fimd_update_plane()
903 val = state->crtc.w * state->crtc.h; in fimd_update_plane()
904 writel(val, ctx->regs + offset); in fimd_update_plane()
906 DRM_DEV_DEBUG_KMS(ctx->dev, "osd size = 0x%x\n", in fimd_update_plane()
910 fimd_win_set_pixfmt(ctx, win, fb, state->src.w); in fimd_update_plane()
918 if (ctx->driver_data->has_shadowcon) in fimd_update_plane()
921 if (ctx->i80_if) in fimd_update_plane()
922 atomic_set(&ctx->win_updated, 1); in fimd_update_plane()
928 struct fimd_context *ctx = crtc->ctx; in fimd_disable_plane()
929 unsigned int win = plane->index; in fimd_disable_plane()
931 if (ctx->suspended) in fimd_disable_plane()
936 if (ctx->driver_data->has_shadowcon) in fimd_disable_plane()
942 struct fimd_context *ctx = crtc->ctx; in fimd_atomic_enable()
944 if (!ctx->suspended) in fimd_atomic_enable()
947 ctx->suspended = false; in fimd_atomic_enable()
949 if (pm_runtime_resume_and_get(ctx->dev) < 0) { in fimd_atomic_enable()
950 dev_warn(ctx->dev, "failed to enable FIMD device.\n"); in fimd_atomic_enable()
955 if (test_and_clear_bit(0, &ctx->irq_flags)) in fimd_atomic_enable()
956 fimd_enable_vblank(ctx->crtc); in fimd_atomic_enable()
958 fimd_commit(ctx->crtc); in fimd_atomic_enable()
963 struct fimd_context *ctx = crtc->ctx; in fimd_atomic_disable()
966 if (ctx->suspended) in fimd_atomic_disable()
975 fimd_disable_plane(crtc, &ctx->planes[i]); in fimd_atomic_disable()
981 writel(0, ctx->regs + VIDCON0); in fimd_atomic_disable()
983 pm_runtime_put_sync(ctx->dev); in fimd_atomic_disable()
984 ctx->suspended = true; in fimd_atomic_disable()
990 const struct fimd_driver_data *driver_data = ctx->driver_data; in fimd_trigger()
991 void *timing_base = ctx->regs + driver_data->timing_base; in fimd_trigger()
998 if (atomic_read(&ctx->triggering)) in fimd_trigger()
1002 atomic_set(&ctx->triggering, 1); in fimd_trigger()
1012 if (!test_bit(0, &ctx->irq_flags)) in fimd_trigger()
1013 atomic_set(&ctx->triggering, 0); in fimd_trigger()
1018 struct fimd_context *ctx = crtc->ctx; in fimd_te_handler()
1019 u32 trg_type = ctx->driver_data->trg_type; in fimd_te_handler()
1022 if (!ctx->drm_dev) in fimd_te_handler()
1032 if (atomic_add_unless(&ctx->win_updated, -1, 0)) in fimd_te_handler()
1033 fimd_trigger(ctx->dev); in fimd_te_handler()
1037 if (atomic_read(&ctx->wait_vsync_event)) { in fimd_te_handler()
1038 atomic_set(&ctx->wait_vsync_event, 0); in fimd_te_handler()
1039 wake_up(&ctx->wait_vsync_queue); in fimd_te_handler()
1042 if (test_bit(0, &ctx->irq_flags)) in fimd_te_handler()
1043 drm_crtc_handle_vblank(&ctx->crtc->base); in fimd_te_handler()
1051 writel(val, ctx->regs + DP_MIE_CLKCON); in fimd_dp_clock_enable()
1072 val = readl(ctx->regs + VIDINTCON1); in fimd_irq_handler()
1074 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; in fimd_irq_handler()
1076 writel(clear_bit, ctx->regs + VIDINTCON1); in fimd_irq_handler()
1079 if (!ctx->drm_dev) in fimd_irq_handler()
1082 if (!ctx->i80_if) in fimd_irq_handler()
1083 drm_crtc_handle_vblank(&ctx->crtc->base); in fimd_irq_handler()
1085 if (ctx->i80_if) { in fimd_irq_handler()
1087 atomic_set(&ctx->triggering, 0); in fimd_irq_handler()
1090 if (atomic_read(&ctx->wait_vsync_event)) { in fimd_irq_handler()
1091 atomic_set(&ctx->wait_vsync_event, 0); in fimd_irq_handler()
1092 wake_up(&ctx->wait_vsync_queue); in fimd_irq_handler()
1108 ctx->drm_dev = drm_dev; in fimd_bind()
1111 if (ctx->driver_data->has_bgr_support) { in fimd_bind()
1112 ctx->configs[i].pixel_formats = fimd_extended_formats; in fimd_bind()
1113 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_extended_formats); in fimd_bind()
1115 ctx->configs[i].pixel_formats = fimd_formats; in fimd_bind()
1116 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats); in fimd_bind()
1119 ctx->configs[i].zpos = i; in fimd_bind()
1120 ctx->configs[i].type = fimd_win_types[i]; in fimd_bind()
1121 ctx->configs[i].capabilities = capabilities[i]; in fimd_bind()
1122 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, in fimd_bind()
1123 &ctx->configs[i]); in fimd_bind()
1128 exynos_plane = &ctx->planes[DEFAULT_WIN]; in fimd_bind()
1129 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, in fimd_bind()
1131 if (IS_ERR(ctx->crtc)) in fimd_bind()
1132 return PTR_ERR(ctx->crtc); in fimd_bind()
1134 if (ctx->driver_data->has_dp_clk) { in fimd_bind()
1135 ctx->dp_clk.enable = fimd_dp_clock_enable; in fimd_bind()
1136 ctx->crtc->pipe_clk = &ctx->dp_clk; in fimd_bind()
1139 if (ctx->encoder) in fimd_bind()
1140 exynos_dpi_bind(drm_dev, ctx->encoder); in fimd_bind()
1145 ret = fimd_clear_channels(ctx->crtc); in fimd_bind()
1150 return exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv); in fimd_bind()
1158 fimd_atomic_disable(ctx->crtc); in fimd_unbind()
1160 exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv); in fimd_unbind()
1162 if (ctx->encoder) in fimd_unbind()
1163 exynos_dpi_remove(ctx->encoder); in fimd_unbind()
1173 struct device *dev = &pdev->dev; in fimd_probe()
1178 if (!dev->of_node) in fimd_probe()
1179 return -ENODEV; in fimd_probe()
1183 return -ENOMEM; in fimd_probe()
1185 ctx->dev = dev; in fimd_probe()
1186 ctx->suspended = true; in fimd_probe()
1187 ctx->driver_data = of_device_get_match_data(dev); in fimd_probe()
1189 if (of_property_read_bool(dev->of_node, "samsung,invert-vden")) in fimd_probe()
1190 ctx->vidcon1 |= VIDCON1_INV_VDEN; in fimd_probe()
1191 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk")) in fimd_probe()
1192 ctx->vidcon1 |= VIDCON1_INV_VCLK; in fimd_probe()
1194 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); in fimd_probe()
1198 ctx->i80_if = true; in fimd_probe()
1200 if (ctx->driver_data->has_vidoutcon) in fimd_probe()
1201 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0; in fimd_probe()
1203 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0; in fimd_probe()
1206 * to enable I80 24-bit data interface. in fimd_probe()
1208 ctx->vidcon0 |= VIDCON0_DSI_EN; in fimd_probe()
1210 if (of_property_read_u32(i80_if_timings, "cs-setup", &val)) in fimd_probe()
1212 ctx->i80ifcon = LCD_CS_SETUP(val); in fimd_probe()
1213 if (of_property_read_u32(i80_if_timings, "wr-setup", &val)) in fimd_probe()
1215 ctx->i80ifcon |= LCD_WR_SETUP(val); in fimd_probe()
1216 if (of_property_read_u32(i80_if_timings, "wr-active", &val)) in fimd_probe()
1218 ctx->i80ifcon |= LCD_WR_ACTIVE(val); in fimd_probe()
1219 if (of_property_read_u32(i80_if_timings, "wr-hold", &val)) in fimd_probe()
1221 ctx->i80ifcon |= LCD_WR_HOLD(val); in fimd_probe()
1225 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, in fimd_probe()
1227 if (IS_ERR(ctx->sysreg)) { in fimd_probe()
1229 ctx->sysreg = NULL; in fimd_probe()
1232 ctx->bus_clk = devm_clk_get(dev, "fimd"); in fimd_probe()
1233 if (IS_ERR(ctx->bus_clk)) { in fimd_probe()
1235 return PTR_ERR(ctx->bus_clk); in fimd_probe()
1238 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); in fimd_probe()
1239 if (IS_ERR(ctx->lcd_clk)) { in fimd_probe()
1241 return PTR_ERR(ctx->lcd_clk); in fimd_probe()
1244 ctx->regs = devm_platform_ioremap_resource(pdev, 0); in fimd_probe()
1245 if (IS_ERR(ctx->regs)) in fimd_probe()
1246 return PTR_ERR(ctx->regs); in fimd_probe()
1248 ret = platform_get_irq_byname(pdev, ctx->i80_if ? "lcd_sys" : "vsync"); in fimd_probe()
1258 init_waitqueue_head(&ctx->wait_vsync_queue); in fimd_probe()
1259 atomic_set(&ctx->wait_vsync_event, 0); in fimd_probe()
1263 ctx->encoder = exynos_dpi_probe(dev); in fimd_probe()
1264 if (IS_ERR(ctx->encoder)) in fimd_probe()
1265 return PTR_ERR(ctx->encoder); in fimd_probe()
1283 pm_runtime_disable(&pdev->dev); in fimd_remove()
1285 component_del(&pdev->dev, &fimd_component_ops); in fimd_remove()
1295 clk_disable_unprepare(ctx->lcd_clk); in exynos_fimd_suspend()
1296 clk_disable_unprepare(ctx->bus_clk); in exynos_fimd_suspend()
1306 ret = clk_prepare_enable(ctx->bus_clk); in exynos_fimd_resume()
1314 ret = clk_prepare_enable(ctx->lcd_clk); in exynos_fimd_resume()
1336 .name = "exynos4-fb",