468 	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |  in etnaviv_gpu_load_clock()
470 	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);  in etnaviv_gpu_load_clock()
508 		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);  in etnaviv_hw_reset()
511 			gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,  in etnaviv_hw_reset()
516 			gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);  in etnaviv_hw_reset()
524 		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);  in etnaviv_hw_reset()
528 		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);  in etnaviv_hw_reset()
551 		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);  in etnaviv_hw_reset()
594 	gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc);  in etnaviv_gpu_enable_mlcg()
631 	gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc);  in etnaviv_gpu_enable_mlcg()
636 	gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);  in etnaviv_gpu_start_fe()
637 	gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,  in etnaviv_gpu_start_fe()
642 		gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL,  in etnaviv_gpu_start_fe()
695 	gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater);  in etnaviv_gpu_setup_pulse_eater()
712 		gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);  in etnaviv_gpu_hw_init()
722 	gpu_write(gpu, VIVS_HI_AXI_CONFIG,  in etnaviv_gpu_hw_init()
733 		gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);  in etnaviv_gpu_hw_init()
739 		gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);  in etnaviv_gpu_hw_init()
745 	gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);  in etnaviv_gpu_hw_init()
1299 	gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);  in sync_point_perfmon_sample_pre()
1304 	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);  in sync_point_perfmon_sample_pre()
1327 	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);  in sync_point_perfmon_sample_post()
1332 	gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);  in sync_point_perfmon_sample_post()