Lines Matching +full:dsi +full:- +full:to +full:- +full:edp
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TC358767/TC358867/TC9595 DSI/DPI-to-DPI/(e)DP bridge driver
6 * All modes are supported -- DPI->(e)DP / DSI->DPI / DSI->(e)DP .
27 #include <linux/media-bus-format.h>
60 /* DSI layer registers */
61 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
65 /* Lane enable PPI and DSI register bits */
79 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
149 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
291 struct mipi_dsi_device *dsi; member
309 /* Input connector type, DSI and not DPI. */
312 /* HPD pin number (0 or 1) or -ENODEV */
338 return regmap_read_poll_timeout(tc->regmap, addr, val, in tc_poll_timeout()
356 ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count); in tc_aux_write_data()
368 ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count); in tc_aux_read_data()
379 u32 auxcfg0 = msg->request; in tc_auxcfg0()
382 auxcfg0 |= FIELD_PREP(DP0_AUXCFG0_BSIZE, size - 1); in tc_auxcfg0()
393 size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size); in tc_aux_transfer()
394 u8 request = msg->request & ~DP_AUX_I2C_MOT; in tc_aux_transfer()
409 ret = tc_aux_write_data(tc, msg->buffer, size); in tc_aux_transfer()
415 return -EINVAL; in tc_aux_transfer()
419 ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address); in tc_aux_transfer()
423 ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size)); in tc_aux_transfer()
431 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus); in tc_aux_transfer()
436 return -ETIMEDOUT; in tc_aux_transfer()
438 * For some reason address-only DP_AUX_I2C_WRITE (MOT), still in tc_aux_transfer()
439 * reports 1 byte transferred in its status. To deal we that in tc_aux_transfer()
441 * address-only transfer in tc_aux_transfer()
445 msg->reply = FIELD_GET(AUX_STATUS, auxstatus); in tc_aux_transfer()
451 return tc_aux_read_data(tc, msg->buffer, size); in tc_aux_transfer()
480 * respect to lane 0 data, AutoCorrect Mode = 0 in tc_srcctrl()
484 if (tc->link.scrambler_dis) in tc_srcctrl()
486 if (tc->link.spread) in tc_srcctrl()
488 if (tc->link.num_lanes == 2) in tc_srcctrl()
490 if (tc->link.rate != 162000) in tc_srcctrl()
499 ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN); in tc_pllupdate()
503 /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */ in tc_pllupdate()
525 * - DPI ..... 0 to 100 MHz in tc_pxl_pll_en()
526 * - (e)DP ... 150 to 650 MHz in tc_pxl_pll_en()
528 if (tc->bridge.type == DRM_MODE_CONNECTOR_DPI) { in tc_pxl_pll_en()
536 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock, in tc_pxl_pll_en()
542 * refclk / ext_pre_div should be in the 1 to 200 MHz range. in tc_pxl_pll_en()
566 delta = clk - pixelclock; in tc_pxl_pll_en()
580 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n", in tc_pxl_pll_en()
582 return -EINVAL; in tc_pxl_pll_en()
585 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock, in tc_pxl_pll_en()
587 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk, in tc_pxl_pll_en()
599 /* Power up PLL and switch to bypass */ in tc_pxl_pll_en()
600 ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN); in tc_pxl_pll_en()
605 pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */ in tc_pxl_pll_en()
606 pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */ in tc_pxl_pll_en()
611 ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam); in tc_pxl_pll_en()
622 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP); in tc_pxl_pll_dis()
634 * to 2^15 or 32,768. in tc_stream_clock_calc()
642 return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768); in tc_stream_clock_calc()
650 rate = clk_get_rate(tc->refclk); in tc_set_syspllparam()
665 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate); in tc_set_syspllparam()
666 return -EINVAL; in tc_set_syspllparam()
669 return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam); in tc_set_syspllparam()
677 /* Setup DP-PHY / PLL */ in tc_aux_link_setup()
682 ret = regmap_write(tc->regmap, DP_PHY_CTRL, in tc_aux_link_setup()
699 if (ret == -ETIMEDOUT) { in tc_aux_link_setup()
700 dev_err(tc->dev, "Timeout waiting for PHY to become ready"); in tc_aux_link_setup()
711 ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1); in tc_aux_link_setup()
716 tc->aux.name = "TC358767 AUX i2c adapter"; in tc_aux_link_setup()
717 tc->aux.dev = tc->dev; in tc_aux_link_setup()
718 tc->aux.transfer = tc_aux_transfer; in tc_aux_link_setup()
719 drm_dp_aux_init(&tc->aux); in tc_aux_link_setup()
723 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret); in tc_aux_link_setup()
735 ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd, in tc_get_display_props()
740 revision = tc->link.dpcd[DP_DPCD_REV]; in tc_get_display_props()
741 rate = drm_dp_max_link_rate(tc->link.dpcd); in tc_get_display_props()
742 num_lanes = drm_dp_max_lane_count(tc->link.dpcd); in tc_get_display_props()
745 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n"); in tc_get_display_props()
749 tc->link.rate = rate; in tc_get_display_props()
752 dev_dbg(tc->dev, "Falling to 2 lanes\n"); in tc_get_display_props()
756 tc->link.num_lanes = num_lanes; in tc_get_display_props()
758 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, ®); in tc_get_display_props()
761 tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5; in tc_get_display_props()
763 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, ®); in tc_get_display_props()
767 tc->link.scrambler_dis = false; in tc_get_display_props()
769 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, ®); in tc_get_display_props()
772 tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; in tc_get_display_props()
774 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n", in tc_get_display_props()
776 (tc->link.rate == 162000) ? "1.62Gbps" : "2.7Gbps", in tc_get_display_props()
777 tc->link.num_lanes, in tc_get_display_props()
778 drm_dp_enhanced_frame_cap(tc->link.dpcd) ? in tc_get_display_props()
780 dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n", in tc_get_display_props()
781 tc->link.spread ? "0.5%" : "0.0%", in tc_get_display_props()
782 tc->link.scrambler_dis ? "disabled" : "enabled"); in tc_get_display_props()
783 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n", in tc_get_display_props()
784 tc->link.assr, tc->assr); in tc_get_display_props()
789 dev_err(tc->dev, "failed to read DPCD: %d\n", ret); in tc_get_display_props()
796 int left_margin = mode->htotal - mode->hsync_end; in tc_set_common_video_mode()
797 int right_margin = mode->hsync_start - mode->hdisplay; in tc_set_common_video_mode()
798 int hsync_len = mode->hsync_end - mode->hsync_start; in tc_set_common_video_mode()
799 int upper_margin = mode->vtotal - mode->vsync_end; in tc_set_common_video_mode()
800 int lower_margin = mode->vsync_start - mode->vdisplay; in tc_set_common_video_mode()
801 int vsync_len = mode->vsync_end - mode->vsync_start; in tc_set_common_video_mode()
804 dev_dbg(tc->dev, "set mode %dx%d\n", in tc_set_common_video_mode()
805 mode->hdisplay, mode->vdisplay); in tc_set_common_video_mode()
806 dev_dbg(tc->dev, "H margin %d,%d sync %d\n", in tc_set_common_video_mode()
808 dev_dbg(tc->dev, "V margin %d,%d sync %d\n", in tc_set_common_video_mode()
810 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal); in tc_set_common_video_mode()
819 ret = regmap_write(tc->regmap, VPCTRL0, in tc_set_common_video_mode()
825 ret = regmap_write(tc->regmap, HTIM01, in tc_set_common_video_mode()
831 ret = regmap_write(tc->regmap, HTIM02, in tc_set_common_video_mode()
832 FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) | in tc_set_common_video_mode()
837 ret = regmap_write(tc->regmap, VTIM01, in tc_set_common_video_mode()
843 ret = regmap_write(tc->regmap, VTIM02, in tc_set_common_video_mode()
845 FIELD_PREP(VDISPR, mode->vdisplay)); in tc_set_common_video_mode()
849 ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */ in tc_set_common_video_mode()
854 ret = regmap_write(tc->regmap, TSTCTL, in tc_set_common_video_mode()
869 if (tc->mode.flags & DRM_MODE_FLAG_NHSYNC) in tc_set_dpi_video_mode()
872 if (tc->mode.flags & DRM_MODE_FLAG_NVSYNC) in tc_set_dpi_video_mode()
875 return regmap_write(tc->regmap, POCTRL, value); in tc_set_dpi_video_mode()
885 int left_margin = mode->htotal - mode->hsync_end; in tc_set_edp_video_mode()
886 int hsync_len = mode->hsync_end - mode->hsync_start; in tc_set_edp_video_mode()
887 int upper_margin = mode->vtotal - mode->vsync_end; in tc_set_edp_video_mode()
888 int vsync_len = mode->vsync_end - mode->vsync_start; in tc_set_edp_video_mode()
901 in_bw = mode->clock * bits_per_pixel / 8; in tc_set_edp_video_mode()
902 out_bw = tc->link.num_lanes * tc->link.rate; in tc_set_edp_video_mode()
906 vid_sync_dly = hsync_len + left_margin + mode->hdisplay; in tc_set_edp_video_mode()
907 ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY, in tc_set_edp_video_mode()
911 ret = regmap_write(tc->regmap, DP0_TOTALVAL, in tc_set_edp_video_mode()
912 FIELD_PREP(H_TOTAL, mode->htotal) | in tc_set_edp_video_mode()
913 FIELD_PREP(V_TOTAL, mode->vtotal)); in tc_set_edp_video_mode()
917 ret = regmap_write(tc->regmap, DP0_STARTVAL, in tc_set_edp_video_mode()
923 ret = regmap_write(tc->regmap, DP0_ACTIVEVAL, in tc_set_edp_video_mode()
924 FIELD_PREP(V_ACT, mode->vdisplay) | in tc_set_edp_video_mode()
925 FIELD_PREP(H_ACT, mode->hdisplay)); in tc_set_edp_video_mode()
932 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in tc_set_edp_video_mode()
935 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in tc_set_edp_video_mode()
938 ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval); in tc_set_edp_video_mode()
944 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in tc_set_edp_video_mode()
947 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in tc_set_edp_video_mode()
950 ret = regmap_write(tc->regmap, DPIPXLFMT, dpipxlfmt); in tc_set_edp_video_mode()
954 ret = regmap_write(tc->regmap, DP0_MISC, in tc_set_edp_video_mode()
969 dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n"); in tc_wait_link_training()
973 ret = regmap_read(tc->regmap, DP0_LTSTAT, &value); in tc_wait_link_training()
982 struct drm_dp_aux *aux = &tc->aux; in tc_main_link_enable()
983 struct device *dev = tc->dev; in tc_main_link_enable()
989 dev_dbg(tc->dev, "link enable\n"); in tc_main_link_enable()
991 ret = regmap_read(tc->regmap, DP0CTL, &value); in tc_main_link_enable()
996 ret = regmap_write(tc->regmap, DP0CTL, 0); in tc_main_link_enable()
1001 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc)); in tc_main_link_enable()
1004 /* SSCG and BW27 on DP1 must be set to the same as on DP0 */ in tc_main_link_enable()
1005 ret = regmap_write(tc->regmap, DP1_SRCCTRL, in tc_main_link_enable()
1006 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) | in tc_main_link_enable()
1007 ((tc->link.rate != 162000) ? DP0_SRCCTRL_BW27 : 0)); in tc_main_link_enable()
1017 if (tc->link.num_lanes == 2) in tc_main_link_enable()
1020 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); in tc_main_link_enable()
1035 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); in tc_main_link_enable()
1038 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); in tc_main_link_enable()
1047 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8); in tc_main_link_enable()
1054 * seems there is no way to change this setting from SW in tc_main_link_enable()
1058 if (tc->assr != tc->link.assr) { in tc_main_link_enable()
1059 dev_dbg(dev, "Trying to set display to ASSR: %d\n", in tc_main_link_enable()
1060 tc->assr); in tc_main_link_enable()
1061 /* try to set ASSR on display side */ in tc_main_link_enable()
1062 tmp[0] = tc->assr; in tc_main_link_enable()
1071 if (tmp[0] != tc->assr) { in tc_main_link_enable()
1072 dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n", in tc_main_link_enable()
1073 tc->assr); in tc_main_link_enable()
1075 tc->link.scrambler_dis = true; in tc_main_link_enable()
1080 tmp[0] = drm_dp_link_rate_to_bw_code(tc->link.rate); in tc_main_link_enable()
1081 tmp[1] = tc->link.num_lanes; in tc_main_link_enable()
1083 if (drm_dp_enhanced_frame_cap(tc->link.dpcd)) in tc_main_link_enable()
1091 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00; in tc_main_link_enable()
1098 /* Reset voltage-swing & pre-emphasis */ in tc_main_link_enable()
1105 /* Clock-Recovery */ in tc_main_link_enable()
1108 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL, in tc_main_link_enable()
1114 ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL, in tc_main_link_enable()
1121 ret = regmap_write(tc->regmap, DP0_SRCCTRL, in tc_main_link_enable()
1128 /* Enable DP0 to start Link Training */ in tc_main_link_enable()
1129 ret = regmap_write(tc->regmap, DP0CTL, in tc_main_link_enable()
1130 (drm_dp_enhanced_frame_cap(tc->link.dpcd) ? in tc_main_link_enable()
1142 dev_err(tc->dev, "Link training phase 1 failed: %s\n", in tc_main_link_enable()
1144 return -ENODEV; in tc_main_link_enable()
1150 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL, in tc_main_link_enable()
1156 ret = regmap_write(tc->regmap, DP0_SRCCTRL, in tc_main_link_enable()
1169 dev_err(tc->dev, "Link training phase 2 failed: %s\n", in tc_main_link_enable()
1171 return -ENODEV; in tc_main_link_enable()
1175 * Toshiba's documentation suggests to first clear DPCD 0x102, then in tc_main_link_enable()
1184 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) | in tc_main_link_enable()
1191 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00; in tc_main_link_enable()
1206 dev_err(tc->dev, "Lane 0 failed: %x\n", value); in tc_main_link_enable()
1207 ret = -ENODEV; in tc_main_link_enable()
1210 if (tc->link.num_lanes == 2) { in tc_main_link_enable()
1214 dev_err(tc->dev, "Lane 1 failed: %x\n", value); in tc_main_link_enable()
1215 ret = -ENODEV; in tc_main_link_enable()
1219 dev_err(tc->dev, "Interlane align failed\n"); in tc_main_link_enable()
1220 ret = -ENODEV; in tc_main_link_enable()
1236 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret); in tc_main_link_enable()
1239 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret); in tc_main_link_enable()
1247 dev_dbg(tc->dev, "link disable\n"); in tc_main_link_disable()
1249 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0); in tc_main_link_disable()
1253 ret = regmap_write(tc->regmap, DP0CTL, 0); in tc_main_link_disable()
1257 return regmap_update_bits(tc->regmap, DP_PHY_CTRL, in tc_main_link_disable()
1267 regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 5); in tc_dsi_rx_enable()
1268 regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 5); in tc_dsi_rx_enable()
1269 regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 5); in tc_dsi_rx_enable()
1270 regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 5); in tc_dsi_rx_enable()
1271 regmap_write(tc->regmap, PPI_D0S_ATMR, 0); in tc_dsi_rx_enable()
1272 regmap_write(tc->regmap, PPI_D1S_ATMR, 0); in tc_dsi_rx_enable()
1273 regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE); in tc_dsi_rx_enable()
1274 regmap_write(tc->regmap, PPI_LPTXTIMECNT, LPX_PERIOD); in tc_dsi_rx_enable()
1276 value = ((LANEENABLE_L0EN << tc->dsi->lanes) - LANEENABLE_L0EN) | in tc_dsi_rx_enable()
1278 regmap_write(tc->regmap, PPI_LANEENABLE, value); in tc_dsi_rx_enable()
1279 regmap_write(tc->regmap, DSI_LANEENABLE, value); in tc_dsi_rx_enable()
1287 ret = regmap_write(tc->regmap, SYSCTRL, value); in tc_dsi_rx_enable()
1293 regmap_write(tc->regmap, PPI_STARTPPI, PPI_START_FUNCTION); in tc_dsi_rx_enable()
1294 regmap_write(tc->regmap, DSI_STARTDSI, DSI_RX_START); in tc_dsi_rx_enable()
1309 return regmap_write(tc->regmap, SYSCTRL, value); in tc_dpi_rx_enable()
1316 dev_dbg(tc->dev, "enable video stream\n"); in tc_dpi_stream_enable()
1336 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), in tc_dpi_stream_enable()
1337 1000 * tc->mode.clock); in tc_dpi_stream_enable()
1341 ret = tc_set_common_video_mode(tc, &tc->mode); in tc_dpi_stream_enable()
1345 ret = tc_set_dpi_video_mode(tc, &tc->mode); in tc_dpi_stream_enable()
1354 dev_dbg(tc->dev, "disable video stream\n"); in tc_dpi_stream_disable()
1366 dev_dbg(tc->dev, "enable video stream\n"); in tc_edp_stream_enable()
1369 * Pixel PLL must be enabled for DSI input mode and test pattern. in tc_edp_stream_enable()
1371 * Per TC9595XBG datasheet Revision 0.1 2018-12-27 Figure 4.18 in tc_edp_stream_enable()
1374 * case valid Pixel Clock are supplied to the chip DPI input. in tc_edp_stream_enable()
1375 * In case built-in test pattern is desired OR DSI input mode in tc_edp_stream_enable()
1379 if (tc->input_connector_dsi || tc_test_pattern) { in tc_edp_stream_enable()
1380 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), in tc_edp_stream_enable()
1381 1000 * tc->mode.clock); in tc_edp_stream_enable()
1386 ret = tc_set_common_video_mode(tc, &tc->mode); in tc_edp_stream_enable()
1390 ret = tc_set_edp_video_mode(tc, &tc->mode); in tc_edp_stream_enable()
1400 if (drm_dp_enhanced_frame_cap(tc->link.dpcd)) in tc_edp_stream_enable()
1402 ret = regmap_write(tc->regmap, DP0CTL, value); in tc_edp_stream_enable()
1407 * cycles from the time VID_MN_GEN is enabled in order to in tc_edp_stream_enable()
1409 * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(), in tc_edp_stream_enable()
1414 ret = regmap_write(tc->regmap, DP0CTL, value); in tc_edp_stream_enable()
1419 if (tc->input_connector_dsi) in tc_edp_stream_enable()
1429 dev_dbg(tc->dev, "disable video stream\n"); in tc_edp_stream_disable()
1431 ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0); in tc_edp_stream_disable()
1450 dev_err(tc->dev, "main link stream start error: %d\n", ret); in tc_dpi_bridge_atomic_enable()
1465 dev_err(tc->dev, "main link stream stop error: %d\n", ret); in tc_dpi_bridge_atomic_disable()
1477 dev_err(tc->dev, "failed to read display props: %d\n", ret); in tc_edp_bridge_atomic_enable()
1483 dev_err(tc->dev, "main link enable error: %d\n", ret); in tc_edp_bridge_atomic_enable()
1489 dev_err(tc->dev, "main link stream start error: %d\n", ret); in tc_edp_bridge_atomic_enable()
1504 dev_err(tc->dev, "main link stream stop error: %d\n", ret); in tc_edp_bridge_atomic_disable()
1508 dev_err(tc->dev, "main link disable error: %d\n", ret); in tc_edp_bridge_atomic_disable()
1516 /* DSI->DPI interface clock limitation: upto 100 MHz */ in tc_dpi_atomic_check()
1517 if (crtc_state->adjusted_mode.clock > 100000) in tc_dpi_atomic_check()
1518 return -EINVAL; in tc_dpi_atomic_check()
1528 /* DPI->(e)DP interface clock limitation: upto 154 MHz */ in tc_edp_atomic_check()
1529 if (crtc_state->adjusted_mode.clock > 154000) in tc_edp_atomic_check()
1530 return -EINVAL; in tc_edp_atomic_check()
1541 if (mode->clock > 100000) in tc_dpi_mode_valid()
1557 if (mode->clock > 154000) in tc_edp_mode_valid()
1560 req = mode->clock * bits_per_pixel / 8; in tc_edp_mode_valid()
1561 avail = tc->link.num_lanes * tc->link.rate; in tc_edp_mode_valid()
1575 drm_mode_copy(&tc->mode, mode); in tc_bridge_mode_set()
1583 return drm_get_edid(connector, &tc->aux.ddc); in tc_get_edid()
1595 dev_err(tc->dev, "failed to read display props: %d\n", ret); in tc_connector_get_modes()
1599 if (tc->panel_bridge) { in tc_connector_get_modes()
1600 num_modes = drm_bridge_get_modes(tc->panel_bridge, connector); in tc_connector_get_modes()
1605 edid = tc_get_edid(&tc->bridge, connector); in tc_connector_get_modes()
1623 ret = regmap_read(tc->regmap, GPIOI, &val); in tc_bridge_detect()
1627 conn = val & BIT(tc->hpd_pin); in tc_bridge_detect()
1640 if (tc->hpd_pin >= 0) in tc_connector_detect()
1641 return tc_bridge_detect(&tc->bridge); in tc_connector_detect()
1643 if (tc->panel_bridge) in tc_connector_detect()
1663 if (!tc->panel_bridge) in tc_dpi_bridge_attach()
1666 return drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge, in tc_dpi_bridge_attach()
1667 &tc->bridge, flags); in tc_dpi_bridge_attach()
1675 struct drm_device *drm = bridge->dev; in tc_edp_bridge_attach()
1678 if (tc->panel_bridge) { in tc_edp_bridge_attach()
1680 ret = drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge, in tc_edp_bridge_attach()
1681 &tc->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR); in tc_edp_bridge_attach()
1689 tc->aux.drm_dev = drm; in tc_edp_bridge_attach()
1690 ret = drm_dp_aux_register(&tc->aux); in tc_edp_bridge_attach()
1694 /* Create DP/eDP connector */ in tc_edp_bridge_attach()
1695 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs); in tc_edp_bridge_attach()
1696 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, tc->bridge.type); in tc_edp_bridge_attach()
1701 if (tc->hpd_pin >= 0) { in tc_edp_bridge_attach()
1702 if (tc->have_irq) in tc_edp_bridge_attach()
1703 tc->connector.polled = DRM_CONNECTOR_POLL_HPD; in tc_edp_bridge_attach()
1705 tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT | in tc_edp_bridge_attach()
1709 drm_display_info_set_bus_formats(&tc->connector.display_info, in tc_edp_bridge_attach()
1711 tc->connector.display_info.bus_flags = in tc_edp_bridge_attach()
1715 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder); in tc_edp_bridge_attach()
1719 drm_dp_aux_unregister(&tc->aux); in tc_edp_bridge_attach()
1725 drm_dp_aux_unregister(&bridge_to_tc(bridge)->aux); in tc_edp_bridge_detach()
1747 /* This is the DSI-end bus format */ in tc_dpi_atomic_get_input_bus_fmts()
1829 r = regmap_read(tc->regmap, INTSTS_G, &val); in tc_irq_handler()
1839 regmap_read(tc->regmap, SYSSTAT, &stat); in tc_irq_handler()
1841 dev_err(tc->dev, "syserr %x\n", stat); in tc_irq_handler()
1844 if (tc->hpd_pin >= 0 && tc->bridge.dev) { in tc_irq_handler()
1851 bool h = val & INT_GPIO_H(tc->hpd_pin); in tc_irq_handler()
1852 bool lc = val & INT_GPIO_LC(tc->hpd_pin); in tc_irq_handler()
1854 dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin, in tc_irq_handler()
1858 drm_kms_helper_hotplug_event(tc->bridge.dev); in tc_irq_handler()
1861 regmap_write(tc->regmap, INTSTS_G, val); in tc_irq_handler()
1868 struct device *dev = tc->dev; in tc_mipi_dsi_host_attach()
1871 struct mipi_dsi_device *dsi; in tc_mipi_dsi_host_attach() local
1880 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1); in tc_mipi_dsi_host_attach()
1888 return -EPROBE_DEFER; in tc_mipi_dsi_host_attach()
1893 dsi = mipi_dsi_device_register_full(host, &info); in tc_mipi_dsi_host_attach()
1894 if (IS_ERR(dsi)) in tc_mipi_dsi_host_attach()
1895 return dev_err_probe(dev, PTR_ERR(dsi), in tc_mipi_dsi_host_attach()
1896 "failed to create dsi device\n"); in tc_mipi_dsi_host_attach()
1898 tc->dsi = dsi; in tc_mipi_dsi_host_attach()
1900 dsi->lanes = dsi_lanes; in tc_mipi_dsi_host_attach()
1901 dsi->format = MIPI_DSI_FMT_RGB888; in tc_mipi_dsi_host_attach()
1902 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE; in tc_mipi_dsi_host_attach()
1904 ret = mipi_dsi_attach(dsi); in tc_mipi_dsi_host_attach()
1906 dev_err(dev, "failed to attach dsi to host: %d\n", ret); in tc_mipi_dsi_host_attach()
1915 struct device *dev = tc->dev; in tc_probe_dpi_bridge_endpoint()
1921 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, &bridge); in tc_probe_dpi_bridge_endpoint()
1922 if (ret && ret != -ENODEV) in tc_probe_dpi_bridge_endpoint()
1932 tc->panel_bridge = bridge; in tc_probe_dpi_bridge_endpoint()
1933 tc->bridge.type = DRM_MODE_CONNECTOR_DPI; in tc_probe_dpi_bridge_endpoint()
1934 tc->bridge.funcs = &tc_dpi_bridge_funcs; in tc_probe_dpi_bridge_endpoint()
1944 struct device *dev = tc->dev; in tc_probe_edp_bridge_endpoint()
1949 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &panel, NULL); in tc_probe_edp_bridge_endpoint()
1950 if (ret && ret != -ENODEV) in tc_probe_edp_bridge_endpoint()
1960 tc->panel_bridge = panel_bridge; in tc_probe_edp_bridge_endpoint()
1961 tc->bridge.type = DRM_MODE_CONNECTOR_eDP; in tc_probe_edp_bridge_endpoint()
1963 tc->bridge.type = DRM_MODE_CONNECTOR_DisplayPort; in tc_probe_edp_bridge_endpoint()
1966 tc->bridge.funcs = &tc_edp_bridge_funcs; in tc_probe_edp_bridge_endpoint()
1967 if (tc->hpd_pin >= 0) in tc_probe_edp_bridge_endpoint()
1968 tc->bridge.ops |= DRM_BRIDGE_OP_DETECT; in tc_probe_edp_bridge_endpoint()
1969 tc->bridge.ops |= DRM_BRIDGE_OP_EDID; in tc_probe_edp_bridge_endpoint()
1976 struct device *dev = tc->dev; in tc_probe_bridge_endpoint()
1990 * port@0 - DSI input in tc_probe_bridge_endpoint()
1991 * port@1 - DPI input/output in tc_probe_bridge_endpoint()
1992 * port@2 - eDP output in tc_probe_bridge_endpoint()
1995 * DPI -> port@1 -> port@2 -> eDP :: [port@0 is not connected] in tc_probe_bridge_endpoint()
1996 * DSI -> port@0 -> port@2 -> eDP :: [port@1 is not connected] in tc_probe_bridge_endpoint()
1997 * DSI -> port@0 -> port@1 -> DPI :: [port@2 is not connected] in tc_probe_bridge_endpoint()
2000 for_each_endpoint_of_node(dev->of_node, node) { in tc_probe_bridge_endpoint()
2004 return -EINVAL; in tc_probe_bridge_endpoint()
2010 tc->input_connector_dsi = false; in tc_probe_bridge_endpoint()
2013 tc->input_connector_dsi = true; in tc_probe_bridge_endpoint()
2016 tc->input_connector_dsi = true; in tc_probe_bridge_endpoint()
2022 return -EINVAL; in tc_probe_bridge_endpoint()
2034 struct device *dev = &client->dev; in tc_probe()
2040 return -ENOMEM; in tc_probe()
2042 tc->dev = dev; in tc_probe()
2048 tc->refclk = devm_clk_get(dev, "ref"); in tc_probe()
2049 if (IS_ERR(tc->refclk)) { in tc_probe()
2050 ret = PTR_ERR(tc->refclk); in tc_probe()
2051 dev_err(dev, "Failed to get refclk: %d\n", ret); in tc_probe()
2055 ret = clk_prepare_enable(tc->refclk); in tc_probe()
2059 ret = devm_add_action_or_reset(dev, tc_clk_disable, tc->refclk); in tc_probe()
2067 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH); in tc_probe()
2068 if (IS_ERR(tc->sd_gpio)) in tc_probe()
2069 return PTR_ERR(tc->sd_gpio); in tc_probe()
2071 if (tc->sd_gpio) { in tc_probe()
2072 gpiod_set_value_cansleep(tc->sd_gpio, 0); in tc_probe()
2077 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); in tc_probe()
2078 if (IS_ERR(tc->reset_gpio)) in tc_probe()
2079 return PTR_ERR(tc->reset_gpio); in tc_probe()
2081 if (tc->reset_gpio) { in tc_probe()
2082 gpiod_set_value_cansleep(tc->reset_gpio, 1); in tc_probe()
2086 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config); in tc_probe()
2087 if (IS_ERR(tc->regmap)) { in tc_probe()
2088 ret = PTR_ERR(tc->regmap); in tc_probe()
2089 dev_err(dev, "Failed to initialize regmap: %d\n", ret); in tc_probe()
2093 ret = of_property_read_u32(dev->of_node, "toshiba,hpd-pin", in tc_probe()
2094 &tc->hpd_pin); in tc_probe()
2096 tc->hpd_pin = -ENODEV; in tc_probe()
2098 if (tc->hpd_pin < 0 || tc->hpd_pin > 1) { in tc_probe()
2099 dev_err(dev, "failed to parse HPD number\n"); in tc_probe()
2104 if (client->irq > 0) { in tc_probe()
2106 regmap_write(tc->regmap, INTCTL_G, INT_SYSERR); in tc_probe()
2108 ret = devm_request_threaded_irq(dev, client->irq, in tc_probe()
2111 "tc358767-irq", tc); in tc_probe()
2113 dev_err(dev, "failed to register dp interrupt\n"); in tc_probe()
2117 tc->have_irq = true; in tc_probe()
2120 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev); in tc_probe()
2122 dev_err(tc->dev, "can not read device ID: %d\n", ret); in tc_probe()
2126 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) { in tc_probe()
2127 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev); in tc_probe()
2128 return -EINVAL; in tc_probe()
2131 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */ in tc_probe()
2133 if (!tc->reset_gpio) { in tc_probe()
2140 regmap_update_bits(tc->regmap, SYSRSTENB, in tc_probe()
2143 regmap_update_bits(tc->regmap, SYSRSTENB, in tc_probe()
2149 if (tc->hpd_pin >= 0) { in tc_probe()
2150 u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT; in tc_probe()
2151 u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin); in tc_probe()
2153 /* Set LCNT to 2ms */ in tc_probe()
2154 regmap_write(tc->regmap, lcnt_reg, in tc_probe()
2155 clk_get_rate(tc->refclk) * 2 / 1000); in tc_probe()
2157 regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin)); in tc_probe()
2159 if (tc->have_irq) { in tc_probe()
2161 regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc); in tc_probe()
2165 if (tc->bridge.type != DRM_MODE_CONNECTOR_DPI) { /* (e)DP output */ in tc_probe()
2171 tc->bridge.of_node = dev->of_node; in tc_probe()
2172 drm_bridge_add(&tc->bridge); in tc_probe()
2176 if (tc->input_connector_dsi) { /* DSI input */ in tc_probe()
2179 drm_bridge_remove(&tc->bridge); in tc_probe()
2191 drm_bridge_remove(&tc->bridge); in tc_remove()
2218 MODULE_DESCRIPTION("tc358767 eDP encoder driver");