Lines Matching refs:FLD_VAL
25 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) macro
45 #define VP_CTRL_MSF(v) FLD_VAL(v, 0, 0) /* Magic square in RGB666 */
46 #define VP_CTRL_VTGEN(v) FLD_VAL(v, 4, 4) /* Use chip clock for timing */
47 #define VP_CTRL_EVTMODE(v) FLD_VAL(v, 5, 5) /* Event mode */
48 #define VP_CTRL_RGB888(v) FLD_VAL(v, 8, 8) /* RGB888 mode */
49 #define VP_CTRL_VSDELAY(v) FLD_VAL(v, 31, 20) /* VSYNC delay */
54 #define VP_HTIM1_HBP(v) FLD_VAL(v, 24, 16)
55 #define VP_HTIM1_HSYNC(v) FLD_VAL(v, 8, 0)
57 #define VP_HTIM2_HFP(v) FLD_VAL(v, 24, 16)
58 #define VP_HTIM2_HACT(v) FLD_VAL(v, 10, 0)
60 #define VP_VTIM1_VBP(v) FLD_VAL(v, 23, 16)
61 #define VP_VTIM1_VSYNC(v) FLD_VAL(v, 7, 0)
63 #define VP_VTIM2_VFP(v) FLD_VAL(v, 23, 16)
64 #define VP_VTIM2_VACT(v) FLD_VAL(v, 10, 0)
75 #define LV_MX(b0, b1, b2, b3) (FLD_VAL(b0, 4, 0) | FLD_VAL(b1, 12, 8) | \
76 FLD_VAL(b2, 20, 16) | FLD_VAL(b3, 28, 24))
112 #define LV_PHY0_RST(v) FLD_VAL(v, 22, 22) /* PHY reset */
113 #define LV_PHY0_IS(v) FLD_VAL(v, 15, 14)
114 #define LV_PHY0_ND(v) FLD_VAL(v, 4, 0) /* Frequency range select */
115 #define LV_PHY0_PRBS_ON(v) FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */