Lines Matching +full:v +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
24 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
28 #define PPI_STARTPPI 0x0104 /* START control bit */
39 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
45 #define VP_CTRL_MSF(v) FLD_VAL(v, 0, 0) /* Magic square in RGB666 */ argument
46 #define VP_CTRL_VTGEN(v) FLD_VAL(v, 4, 4) /* Use chip clock for timing */ argument
47 #define VP_CTRL_EVTMODE(v) FLD_VAL(v, 5, 5) /* Event mode */ argument
48 #define VP_CTRL_RGB888(v) FLD_VAL(v, 8, 8) /* RGB888 mode */ argument
49 #define VP_CTRL_VSDELAY(v) FLD_VAL(v, 31, 20) /* VSYNC delay */ argument
50 #define VP_CTRL_HSPOL BIT(17) /* Polarity of HSYNC signal */
51 #define VP_CTRL_DEPOL BIT(18) /* Polarity of DE signal */
52 #define VP_CTRL_VSPOL BIT(19) /* Polarity of VSYNC signal */
54 #define VP_HTIM1_HBP(v) FLD_VAL(v, 24, 16) argument
55 #define VP_HTIM1_HSYNC(v) FLD_VAL(v, 8, 0) argument
57 #define VP_HTIM2_HFP(v) FLD_VAL(v, 24, 16) argument
58 #define VP_HTIM2_HACT(v) FLD_VAL(v, 10, 0) argument
60 #define VP_VTIM1_VBP(v) FLD_VAL(v, 23, 16) argument
61 #define VP_VTIM1_VSYNC(v) FLD_VAL(v, 7, 0) argument
63 #define VP_VTIM2_VFP(v) FLD_VAL(v, 23, 16) argument
64 #define VP_VTIM2_VACT(v) FLD_VAL(v, 10, 0) argument
68 #define LV_MX0003 0x0480 /* Mux input bit 0 to 3 */
69 #define LV_MX0407 0x0484 /* Mux input bit 4 to 7 */
70 #define LV_MX0811 0x0488 /* Mux input bit 8 to 11 */
71 #define LV_MX1215 0x048C /* Mux input bit 12 to 15 */
72 #define LV_MX1619 0x0490 /* Mux input bit 16 to 19 */
73 #define LV_MX2023 0x0494 /* Mux input bit 20 to 23 */
74 #define LV_MX2427 0x0498 /* Mux input bit 24 to 27 */
78 /* Input bit numbers used in mux registers */
112 #define LV_PHY0_RST(v) FLD_VAL(v, 22, 22) /* PHY reset */ argument
113 #define LV_PHY0_IS(v) FLD_VAL(v, 15, 14) argument
114 #define LV_PHY0_ND(v) FLD_VAL(v, 4, 0) /* Frequency range select */ argument
115 #define LV_PHY0_PRBS_ON(v) FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */ argument
121 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
122 #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */
123 #define SYS_RST_LCD BIT(2) /* Reset LCD controller */
124 #define SYS_RST_BM BIT(3) /* Reset Bus Management controller */
125 #define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */
126 #define SYS_RST_REG BIT(5) /* Reset Register module */
133 #define LANEENABLE_CLEN BIT(0)
134 #define LANEENABLE_L0EN BIT(1)
135 #define LANEENABLE_L1EN BIT(2)
136 #define LANEENABLE_L2EN BIT(3)
137 #define LANEENABLE_L3EN BIT(4)
140 #define LV_CFG_LVEN BIT(0)
141 #define LV_CFG_LVDLINK BIT(1)
142 #define LV_CFG_CLKPOL1 BIT(2)
143 #define LV_CFG_CLKPOL2 BIT(3)
160 int ret = ctx->error; in tc358764_clear_error()
162 ctx->error = 0; in tc358764_clear_error()
168 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); in tc358764_read()
171 if (ctx->error) in tc358764_read()
179 dev_dbg(ctx->dev, "read: %d, addr: %d\n", addr, *val); in tc358764_read()
184 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); in tc358764_write()
188 if (ctx->error) in tc358764_write()
200 ctx->error = ret; in tc358764_write()
210 u32 v = 0; in tc358764_init() local
212 tc358764_read(ctx, SYS_ID, &v); in tc358764_init()
213 if (ctx->error) in tc358764_init()
215 dev_info(ctx->dev, "ID: %#x\n", v); in tc358764_init()
248 /* set bit order */ in tc358764_init()
264 gpiod_set_value(ctx->gpio_reset, 1); in tc358764_reset()
266 gpiod_set_value(ctx->gpio_reset, 0); in tc358764_reset()
277 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); in tc358764_post_disable()
279 dev_err(ctx->dev, "error disabling regulators (%d)\n", ret); in tc358764_post_disable()
287 ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); in tc358764_pre_enable()
289 dev_err(ctx->dev, "error enabling regulators (%d)\n", ret); in tc358764_pre_enable()
294 dev_err(ctx->dev, "error initializing bridge (%d)\n", ret); in tc358764_pre_enable()
302 return drm_bridge_attach(bridge->encoder, ctx->next_bridge, bridge, flags); in tc358764_attach()
313 struct device *dev = ctx->dev; in tc358764_parse_dt()
315 ctx->gpio_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); in tc358764_parse_dt()
316 if (IS_ERR(ctx->gpio_reset)) { in tc358764_parse_dt()
318 return PTR_ERR(ctx->gpio_reset); in tc358764_parse_dt()
321 ctx->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0); in tc358764_parse_dt()
322 if (IS_ERR(ctx->next_bridge)) in tc358764_parse_dt()
323 return PTR_ERR(ctx->next_bridge); in tc358764_parse_dt()
332 for (i = 0; i < ARRAY_SIZE(ctx->supplies); ++i) in tc358764_configure_regulators()
333 ctx->supplies[i].supply = tc358764_supplies[i]; in tc358764_configure_regulators()
335 ret = devm_regulator_bulk_get(ctx->dev, ARRAY_SIZE(ctx->supplies), in tc358764_configure_regulators()
336 ctx->supplies); in tc358764_configure_regulators()
338 dev_err(ctx->dev, "failed to get regulators: %d\n", ret); in tc358764_configure_regulators()
345 struct device *dev = &dsi->dev; in tc358764_probe()
351 return -ENOMEM; in tc358764_probe()
355 ctx->dev = dev; in tc358764_probe()
357 dsi->lanes = 4; in tc358764_probe()
358 dsi->format = MIPI_DSI_FMT_RGB888; in tc358764_probe()
359 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST in tc358764_probe()
370 ctx->bridge.funcs = &tc358764_bridge_funcs; in tc358764_probe()
371 ctx->bridge.of_node = dev->of_node; in tc358764_probe()
373 drm_bridge_add(&ctx->bridge); in tc358764_probe()
377 drm_bridge_remove(&ctx->bridge); in tc358764_probe()
389 drm_bridge_remove(&ctx->bridge); in tc358764_remove()
411 MODULE_DESCRIPTION("MIPI-DSI based Driver for TC358764 DSI/LVDS Bridge");