Lines Matching +full:tdm +full:- +full:data +full:- +full:delay

1 /* SPDX-License-Identifier: GPL-2.0-only */
9  * Copyright (C) 2013-2014 Silicon Image, Inc.
273 /* DDC I2C Data In count #1, default value: 0x00 */
276 /* DDC I2C Data In count #2, default value: 0x00 */
301 /* DDC I2C FIFO Data In/Out, default value: 0x00 */
304 /* DDC I2C Data Out Counter, default value: 0x00 */
309 /* DDC I2C Delay Count, default value: 0x14 */
323 /* I2C Device Address re-assignment */
349 /* TDM TX NUMBITS, default value: 0x0c */
355 /* TDM TX NUMSPISYM, default value: 0x04 */
358 /* TDM TX NUMHSICSYM, default value: 0x14 */
361 /* TDM TX NUMTOTSYM, default value: 0x18 */
364 /* TDM TX INT Low, default value: 0x00 */
375 /* TDM TX INT High, default value: 0x00 */
386 /* TDM RX Control, default value: 0x1c */
392 /* TDM RX NUMSPISYM, default value: 0x04 */
395 /* TDM RX NUMHSICSYM, default value: 0x14 */
398 /* TDM RX NUMTOTSYM, default value: 0x18 */
401 /* TDM RX Status 2nd, default value: 0x00 */
406 /* TDM RX INT Low, default value: 0x00 */
409 /* TDM RX INT High, default value: 0x00 */
414 /* TDM RX INTMASK High, default value: 0x00 */
464 /* TDM Low Latency, default value: 0x20 */
614 /* EDID FIFO Write Data, default value: 0x00 */
620 /* EDID FIFO Read Data, default value: 0x00 */
648 /* E-MSC General Control, default value: 0x80 */
659 /* E-MSC Comma ErrorCNT, default value: 0x03 */
664 /* E-MSC RFIFO ByteCnt, default value: 0x00 */
678 /* E-MSC 1st Interrupt, default value: 0x00 */
689 /* E-MSC Interrupt Mask, default value: 0x00 */
692 /* I2C E-MSC XMIT FIFO Write Port, default value: 0x00 */
695 /* I2C E-MSC RCV FIFO Write Port, default value: 0x00 */
698 /* E-MSC 2nd Interrupt, default value: 0x00 */
702 /* E-MSC Interrupt Mask, default value: 0x00 */
1026 /* TPI COPP Query Data, default value: 0x00 */
1040 /* TPI COPP Control Data, default value: 0x00 */
1423 /* CBUS MSC Transmit Data */
1427 /* CBUS MSC Requester Received Data */
1431 /* CBUS MSC Responder MSC_MSG Received Data */