Lines Matching full:dsi
3 * i.MX8 NWL MIPI DSI host driver
34 #include "nwl-dsi.h"
36 #define DRV_NAME "nwl-dsi"
77 * The DSI host controller needs this reset sequence according to NWL:
78 * 1. Deassert pclk reset to get access to DSI regs
79 * 2. Configure DSI Host and DPHY and enable DPHY
81 * 4. Send DSI cmds to configure peripheral (handled by panel drv)
83 * DSI data
85 * TODO: Since panel_bridges do their DSI setup in enable we
94 /* DSI clocks */
105 /* dsi lanes */
128 static int nwl_dsi_clear_error(struct nwl_dsi *dsi) in nwl_dsi_clear_error() argument
130 int ret = dsi->error; in nwl_dsi_clear_error()
132 dsi->error = 0; in nwl_dsi_clear_error()
136 static void nwl_dsi_write(struct nwl_dsi *dsi, unsigned int reg, u32 val) in nwl_dsi_write() argument
140 if (dsi->error) in nwl_dsi_write()
143 ret = regmap_write(dsi->regmap, reg, val); in nwl_dsi_write()
145 DRM_DEV_ERROR(dsi->dev, in nwl_dsi_write()
146 "Failed to write NWL DSI reg 0x%x: %d\n", reg, in nwl_dsi_write()
148 dsi->error = ret; in nwl_dsi_write()
152 static u32 nwl_dsi_read(struct nwl_dsi *dsi, u32 reg) in nwl_dsi_read() argument
157 if (dsi->error) in nwl_dsi_read()
160 ret = regmap_read(dsi->regmap, reg, &val); in nwl_dsi_read()
162 DRM_DEV_ERROR(dsi->dev, "Failed to read NWL DSI reg 0x%x: %d\n", in nwl_dsi_read()
164 dsi->error = ret; in nwl_dsi_read()
188 static u32 ps2bc(struct nwl_dsi *dsi, unsigned long long ps) in ps2bc() argument
190 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); in ps2bc()
192 return DIV64_U64_ROUND_UP(ps * dsi->mode.clock * bpp, in ps2bc()
193 dsi->lanes * 8ULL * NSEC_PER_SEC); in ps2bc()
212 static int nwl_dsi_config_host(struct nwl_dsi *dsi) in nwl_dsi_config_host() argument
215 struct phy_configure_opts_mipi_dphy *cfg = &dsi->phy_cfg.mipi_dphy; in nwl_dsi_config_host()
217 if (dsi->lanes < 1 || dsi->lanes > 4) in nwl_dsi_config_host()
220 DRM_DEV_DEBUG_DRIVER(dsi->dev, "DSI Lanes %d\n", dsi->lanes); in nwl_dsi_config_host()
221 nwl_dsi_write(dsi, NWL_DSI_CFG_NUM_LANES, dsi->lanes - 1); in nwl_dsi_config_host()
223 if (dsi->dsi_mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { in nwl_dsi_config_host()
224 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x01); in nwl_dsi_config_host()
225 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x01); in nwl_dsi_config_host()
227 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x00); in nwl_dsi_config_host()
228 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x00); in nwl_dsi_config_host()
233 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_pre: 0x%x\n", cycles); in nwl_dsi_config_host()
234 nwl_dsi_write(dsi, NWL_DSI_CFG_T_PRE, cycles); in nwl_dsi_config_host()
235 cycles = ps2bc(dsi, cfg->lpx + cfg->clk_prepare + cfg->clk_zero); in nwl_dsi_config_host()
236 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap (pre): 0x%x\n", cycles); in nwl_dsi_config_host()
238 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_post: 0x%x\n", cycles); in nwl_dsi_config_host()
239 nwl_dsi_write(dsi, NWL_DSI_CFG_T_POST, cycles); in nwl_dsi_config_host()
240 cycles = ps2bc(dsi, cfg->hs_exit); in nwl_dsi_config_host()
241 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap: 0x%x\n", cycles); in nwl_dsi_config_host()
242 nwl_dsi_write(dsi, NWL_DSI_CFG_TX_GAP, cycles); in nwl_dsi_config_host()
244 nwl_dsi_write(dsi, NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP, 0x01); in nwl_dsi_config_host()
245 nwl_dsi_write(dsi, NWL_DSI_CFG_HTX_TO_COUNT, 0x00); in nwl_dsi_config_host()
246 nwl_dsi_write(dsi, NWL_DSI_CFG_LRX_H_TO_COUNT, 0x00); in nwl_dsi_config_host()
247 nwl_dsi_write(dsi, NWL_DSI_CFG_BTA_H_TO_COUNT, 0x00); in nwl_dsi_config_host()
250 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_twakeup: 0x%x\n", cycles); in nwl_dsi_config_host()
251 nwl_dsi_write(dsi, NWL_DSI_CFG_TWAKEUP, cycles); in nwl_dsi_config_host()
253 return nwl_dsi_clear_error(dsi); in nwl_dsi_config_host()
256 static int nwl_dsi_config_dpi(struct nwl_dsi *dsi) in nwl_dsi_config_dpi() argument
264 hfront_porch = dsi->mode.hsync_start - dsi->mode.hdisplay; in nwl_dsi_config_dpi()
265 hsync_len = dsi->mode.hsync_end - dsi->mode.hsync_start; in nwl_dsi_config_dpi()
266 hback_porch = dsi->mode.htotal - dsi->mode.hsync_end; in nwl_dsi_config_dpi()
268 vfront_porch = dsi->mode.vsync_start - dsi->mode.vdisplay; in nwl_dsi_config_dpi()
269 vsync_len = dsi->mode.vsync_end - dsi->mode.vsync_start; in nwl_dsi_config_dpi()
270 vback_porch = dsi->mode.vtotal - dsi->mode.vsync_end; in nwl_dsi_config_dpi()
272 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hfront_porch = %d\n", hfront_porch); in nwl_dsi_config_dpi()
273 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hback_porch = %d\n", hback_porch); in nwl_dsi_config_dpi()
274 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hsync_len = %d\n", hsync_len); in nwl_dsi_config_dpi()
275 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hdisplay = %d\n", dsi->mode.hdisplay); in nwl_dsi_config_dpi()
276 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vfront_porch = %d\n", vfront_porch); in nwl_dsi_config_dpi()
277 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vback_porch = %d\n", vback_porch); in nwl_dsi_config_dpi()
278 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vsync_len = %d\n", vsync_len); in nwl_dsi_config_dpi()
279 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vactive = %d\n", dsi->mode.vdisplay); in nwl_dsi_config_dpi()
280 DRM_DEV_DEBUG_DRIVER(dsi->dev, "clock = %d kHz\n", dsi->mode.clock); in nwl_dsi_config_dpi()
282 color_format = nwl_dsi_get_dpi_pixel_format(dsi->format); in nwl_dsi_config_dpi()
284 DRM_DEV_ERROR(dsi->dev, "Invalid color format 0x%x\n", in nwl_dsi_config_dpi()
285 dsi->format); in nwl_dsi_config_dpi()
288 DRM_DEV_DEBUG_DRIVER(dsi->dev, "pixel fmt = %d\n", dsi->format); in nwl_dsi_config_dpi()
290 nwl_dsi_write(dsi, NWL_DSI_INTERFACE_COLOR_CODING, NWL_DSI_DPI_24_BIT); in nwl_dsi_config_dpi()
291 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FORMAT, color_format); in nwl_dsi_config_dpi()
296 nwl_dsi_write(dsi, NWL_DSI_VSYNC_POLARITY, in nwl_dsi_config_dpi()
298 nwl_dsi_write(dsi, NWL_DSI_HSYNC_POLARITY, in nwl_dsi_config_dpi()
301 burst_mode = (dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_BURST) && in nwl_dsi_config_dpi()
302 !(dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE); in nwl_dsi_config_dpi()
305 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, NWL_DSI_VM_BURST_MODE); in nwl_dsi_config_dpi()
306 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL, 256); in nwl_dsi_config_dpi()
308 mode = ((dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) ? in nwl_dsi_config_dpi()
311 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, mode); in nwl_dsi_config_dpi()
312 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL, in nwl_dsi_config_dpi()
313 dsi->mode.hdisplay); in nwl_dsi_config_dpi()
316 nwl_dsi_write(dsi, NWL_DSI_HFP, hfront_porch); in nwl_dsi_config_dpi()
317 nwl_dsi_write(dsi, NWL_DSI_HBP, hback_porch); in nwl_dsi_config_dpi()
318 nwl_dsi_write(dsi, NWL_DSI_HSA, hsync_len); in nwl_dsi_config_dpi()
320 nwl_dsi_write(dsi, NWL_DSI_ENABLE_MULT_PKTS, 0x0); in nwl_dsi_config_dpi()
321 nwl_dsi_write(dsi, NWL_DSI_BLLP_MODE, 0x1); in nwl_dsi_config_dpi()
322 nwl_dsi_write(dsi, NWL_DSI_USE_NULL_PKT_BLLP, 0x0); in nwl_dsi_config_dpi()
323 nwl_dsi_write(dsi, NWL_DSI_VC, 0x0); in nwl_dsi_config_dpi()
325 nwl_dsi_write(dsi, NWL_DSI_PIXEL_PAYLOAD_SIZE, dsi->mode.hdisplay); in nwl_dsi_config_dpi()
326 nwl_dsi_write(dsi, NWL_DSI_VACTIVE, dsi->mode.vdisplay - 1); in nwl_dsi_config_dpi()
327 nwl_dsi_write(dsi, NWL_DSI_VBP, vback_porch); in nwl_dsi_config_dpi()
328 nwl_dsi_write(dsi, NWL_DSI_VFP, vfront_porch); in nwl_dsi_config_dpi()
330 return nwl_dsi_clear_error(dsi); in nwl_dsi_config_dpi()
333 static int nwl_dsi_init_interrupts(struct nwl_dsi *dsi) in nwl_dsi_init_interrupts() argument
340 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, irq_enable); in nwl_dsi_init_interrupts()
341 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK2, 0x7); in nwl_dsi_init_interrupts()
343 return nwl_dsi_clear_error(dsi); in nwl_dsi_init_interrupts()
349 struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host); in nwl_dsi_host_attach() local
350 struct device *dev = dsi->dev; in nwl_dsi_host_attach()
358 dsi->lanes = device->lanes; in nwl_dsi_host_attach()
359 dsi->format = device->format; in nwl_dsi_host_attach()
360 dsi->dsi_mode_flags = device->mode_flags; in nwl_dsi_host_attach()
365 static bool nwl_dsi_read_packet(struct nwl_dsi *dsi, u32 status) in nwl_dsi_read_packet() argument
367 struct device *dev = dsi->dev; in nwl_dsi_read_packet()
368 struct nwl_dsi_transfer *xfer = dsi->xfer; in nwl_dsi_read_packet()
382 val = nwl_dsi_read(dsi, NWL_DSI_RX_PKT_HEADER); in nwl_dsi_read_packet()
383 err = nwl_dsi_clear_error(dsi); in nwl_dsi_read_packet()
418 DRM_DEV_ERROR(dev, "[%02X] DSI error report: 0x%02x\n", in nwl_dsi_read_packet()
444 val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD); in nwl_dsi_read_packet()
455 val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD); in nwl_dsi_read_packet()
473 err = nwl_dsi_clear_error(dsi); in nwl_dsi_read_packet()
480 static void nwl_dsi_finish_transmission(struct nwl_dsi *dsi, u32 status) in nwl_dsi_finish_transmission() argument
482 struct nwl_dsi_transfer *xfer = dsi->xfer; in nwl_dsi_finish_transmission()
495 end_packet = nwl_dsi_read_packet(dsi, status); in nwl_dsi_finish_transmission()
502 static void nwl_dsi_begin_transmission(struct nwl_dsi *dsi) in nwl_dsi_begin_transmission() argument
504 struct nwl_dsi_transfer *xfer = dsi->xfer; in nwl_dsi_begin_transmission()
520 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val); in nwl_dsi_begin_transmission()
536 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val); in nwl_dsi_begin_transmission()
548 if (hs_workaround && (dsi->quirks & E11418_HS_MODE_QUIRK)) { in nwl_dsi_begin_transmission()
549 DRM_DEV_DEBUG_DRIVER(dsi->dev, in nwl_dsi_begin_transmission()
559 nwl_dsi_write(dsi, NWL_DSI_PKT_CONTROL, val); in nwl_dsi_begin_transmission()
562 nwl_dsi_write(dsi, NWL_DSI_SEND_PACKET, 0x1); in nwl_dsi_begin_transmission()
568 struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host); in nwl_dsi_host_transfer() local
573 dsi->xfer = &xfer; in nwl_dsi_host_transfer()
576 dsi->xfer = NULL; in nwl_dsi_host_transfer()
600 ret = clk_prepare_enable(dsi->rx_esc_clk); in nwl_dsi_host_transfer()
602 DRM_DEV_ERROR(dsi->dev, "Failed to enable rx_esc clk: %zd\n", in nwl_dsi_host_transfer()
606 DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled rx_esc clk @%lu Hz\n", in nwl_dsi_host_transfer()
607 clk_get_rate(dsi->rx_esc_clk)); in nwl_dsi_host_transfer()
609 /* Initiate the DSI packet transmision */ in nwl_dsi_host_transfer()
610 nwl_dsi_begin_transmission(dsi); in nwl_dsi_host_transfer()
614 DRM_DEV_ERROR(dsi_host->dev, "[%02X] DSI transfer timed out\n", in nwl_dsi_host_transfer()
621 clk_disable_unprepare(dsi->rx_esc_clk); in nwl_dsi_host_transfer()
634 struct nwl_dsi *dsi = data; in nwl_dsi_irq_handler() local
636 irq_status = nwl_dsi_read(dsi, NWL_DSI_IRQ_STATUS); in nwl_dsi_irq_handler()
639 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "tx fifo overflow\n"); in nwl_dsi_irq_handler()
642 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "HS tx timeout\n"); in nwl_dsi_irq_handler()
647 nwl_dsi_finish_transmission(dsi, irq_status); in nwl_dsi_irq_handler()
652 static int nwl_dsi_mode_set(struct nwl_dsi *dsi) in nwl_dsi_mode_set() argument
654 struct device *dev = dsi->dev; in nwl_dsi_mode_set()
655 union phy_configure_opts *phy_cfg = &dsi->phy_cfg; in nwl_dsi_mode_set()
658 if (!dsi->lanes) { in nwl_dsi_mode_set()
659 DRM_DEV_ERROR(dev, "Need DSI lanes: %d\n", dsi->lanes); in nwl_dsi_mode_set()
663 ret = phy_init(dsi->phy); in nwl_dsi_mode_set()
665 DRM_DEV_ERROR(dev, "Failed to init DSI phy: %d\n", ret); in nwl_dsi_mode_set()
669 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); in nwl_dsi_mode_set()
671 DRM_DEV_ERROR(dev, "Failed to set DSI phy mode: %d\n", ret); in nwl_dsi_mode_set()
675 ret = phy_configure(dsi->phy, phy_cfg); in nwl_dsi_mode_set()
677 DRM_DEV_ERROR(dev, "Failed to configure DSI phy: %d\n", ret); in nwl_dsi_mode_set()
681 ret = clk_prepare_enable(dsi->tx_esc_clk); in nwl_dsi_mode_set()
683 DRM_DEV_ERROR(dsi->dev, "Failed to enable tx_esc clk: %d\n", in nwl_dsi_mode_set()
687 DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled tx_esc clk @%lu Hz\n", in nwl_dsi_mode_set()
688 clk_get_rate(dsi->tx_esc_clk)); in nwl_dsi_mode_set()
690 ret = nwl_dsi_config_host(dsi); in nwl_dsi_mode_set()
692 DRM_DEV_ERROR(dev, "Failed to set up DSI: %d", ret); in nwl_dsi_mode_set()
696 ret = nwl_dsi_config_dpi(dsi); in nwl_dsi_mode_set()
702 ret = phy_power_on(dsi->phy); in nwl_dsi_mode_set()
708 ret = nwl_dsi_init_interrupts(dsi); in nwl_dsi_mode_set()
715 phy_power_off(dsi->phy); in nwl_dsi_mode_set()
717 clk_disable_unprepare(dsi->tx_esc_clk); in nwl_dsi_mode_set()
719 phy_exit(dsi->phy); in nwl_dsi_mode_set()
724 static int nwl_dsi_disable(struct nwl_dsi *dsi) in nwl_dsi_disable() argument
726 struct device *dev = dsi->dev; in nwl_dsi_disable()
730 phy_power_off(dsi->phy); in nwl_dsi_disable()
731 phy_exit(dsi->phy); in nwl_dsi_disable()
733 /* Disabling the clock before the phy breaks enabling dsi again */ in nwl_dsi_disable()
734 clk_disable_unprepare(dsi->tx_esc_clk); in nwl_dsi_disable()
743 struct nwl_dsi *dsi = bridge_to_dsi(bridge); in nwl_dsi_bridge_atomic_disable() local
746 nwl_dsi_disable(dsi); in nwl_dsi_bridge_atomic_disable()
748 ret = reset_control_assert(dsi->rst_dpi); in nwl_dsi_bridge_atomic_disable()
750 DRM_DEV_ERROR(dsi->dev, "Failed to assert DPI: %d\n", ret); in nwl_dsi_bridge_atomic_disable()
753 ret = reset_control_assert(dsi->rst_byte); in nwl_dsi_bridge_atomic_disable()
755 DRM_DEV_ERROR(dsi->dev, "Failed to assert ESC: %d\n", ret); in nwl_dsi_bridge_atomic_disable()
758 ret = reset_control_assert(dsi->rst_esc); in nwl_dsi_bridge_atomic_disable()
760 DRM_DEV_ERROR(dsi->dev, "Failed to assert BYTE: %d\n", ret); in nwl_dsi_bridge_atomic_disable()
763 ret = reset_control_assert(dsi->rst_pclk); in nwl_dsi_bridge_atomic_disable()
765 DRM_DEV_ERROR(dsi->dev, "Failed to assert PCLK: %d\n", ret); in nwl_dsi_bridge_atomic_disable()
769 clk_disable_unprepare(dsi->core_clk); in nwl_dsi_bridge_atomic_disable()
770 clk_disable_unprepare(dsi->lcdif_clk); in nwl_dsi_bridge_atomic_disable()
772 pm_runtime_put(dsi->dev); in nwl_dsi_bridge_atomic_disable()
775 static int nwl_dsi_get_dphy_params(struct nwl_dsi *dsi, in nwl_dsi_get_dphy_params() argument
782 if (dsi->lanes < 1 || dsi->lanes > 4) in nwl_dsi_get_dphy_params()
787 * dphy and nwl dsi host in nwl_dsi_get_dphy_params()
790 mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes, in nwl_dsi_get_dphy_params()
795 rate = clk_get_rate(dsi->tx_esc_clk); in nwl_dsi_get_dphy_params()
796 DRM_DEV_DEBUG_DRIVER(dsi->dev, "LP clk is @%lu Hz\n", rate); in nwl_dsi_get_dphy_params()
807 struct nwl_dsi *dsi = bridge_to_dsi(bridge); in nwl_dsi_bridge_mode_valid() local
808 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); in nwl_dsi_bridge_mode_valid()
810 if (mode->clock * bpp > 15000000 * dsi->lanes) in nwl_dsi_bridge_mode_valid()
813 if (mode->clock * bpp < 80000 * dsi->lanes) in nwl_dsi_bridge_mode_valid()
832 * This ensures our ->mode_set() is called to get the DSI controller in nwl_dsi_bridge_atomic_check()
847 struct nwl_dsi *dsi = bridge_to_dsi(bridge); in nwl_dsi_bridge_mode_set() local
848 struct device *dev = dsi->dev; in nwl_dsi_bridge_mode_set()
853 ret = nwl_dsi_get_dphy_params(dsi, adjusted_mode, &new_cfg); in nwl_dsi_bridge_mode_set()
857 phy_ref_rate = clk_get_rate(dsi->phy_ref_clk); in nwl_dsi_bridge_mode_set()
860 memcpy(&dsi->phy_cfg, &new_cfg, sizeof(new_cfg)); in nwl_dsi_bridge_mode_set()
862 drm_mode_copy(&dsi->mode, adjusted_mode); in nwl_dsi_bridge_mode_set()
868 if (clk_prepare_enable(dsi->lcdif_clk) < 0) in nwl_dsi_bridge_mode_set()
870 if (clk_prepare_enable(dsi->core_clk) < 0) in nwl_dsi_bridge_mode_set()
873 /* Step 1 from DSI reset-out instructions */ in nwl_dsi_bridge_mode_set()
874 ret = reset_control_deassert(dsi->rst_pclk); in nwl_dsi_bridge_mode_set()
880 /* Step 2 from DSI reset-out instructions */ in nwl_dsi_bridge_mode_set()
881 nwl_dsi_mode_set(dsi); in nwl_dsi_bridge_mode_set()
883 /* Step 3 from DSI reset-out instructions */ in nwl_dsi_bridge_mode_set()
884 ret = reset_control_deassert(dsi->rst_esc); in nwl_dsi_bridge_mode_set()
889 ret = reset_control_deassert(dsi->rst_byte); in nwl_dsi_bridge_mode_set()
905 struct nwl_dsi *dsi = bridge_to_dsi(bridge); in nwl_dsi_bridge_atomic_enable() local
908 /* Step 5 from DSI reset-out instructions */ in nwl_dsi_bridge_atomic_enable()
909 ret = reset_control_deassert(dsi->rst_dpi); in nwl_dsi_bridge_atomic_enable()
911 DRM_DEV_ERROR(dsi->dev, "Failed to deassert DPI: %d\n", ret); in nwl_dsi_bridge_atomic_enable()
917 struct nwl_dsi *dsi = bridge_to_dsi(bridge); in nwl_dsi_bridge_attach() local
920 panel_bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node, 1, 0); in nwl_dsi_bridge_attach()
974 static int nwl_dsi_parse_dt(struct nwl_dsi *dsi) in nwl_dsi_parse_dt() argument
976 struct platform_device *pdev = to_platform_device(dsi->dev); in nwl_dsi_parse_dt()
981 dsi->phy = devm_phy_get(dsi->dev, "dphy"); in nwl_dsi_parse_dt()
982 if (IS_ERR(dsi->phy)) { in nwl_dsi_parse_dt()
983 ret = PTR_ERR(dsi->phy); in nwl_dsi_parse_dt()
985 DRM_DEV_ERROR(dsi->dev, "Could not get PHY: %d\n", ret); in nwl_dsi_parse_dt()
989 clk = devm_clk_get(dsi->dev, "lcdif"); in nwl_dsi_parse_dt()
992 DRM_DEV_ERROR(dsi->dev, "Failed to get lcdif clock: %d\n", in nwl_dsi_parse_dt()
996 dsi->lcdif_clk = clk; in nwl_dsi_parse_dt()
998 clk = devm_clk_get(dsi->dev, "core"); in nwl_dsi_parse_dt()
1001 DRM_DEV_ERROR(dsi->dev, "Failed to get core clock: %d\n", in nwl_dsi_parse_dt()
1005 dsi->core_clk = clk; in nwl_dsi_parse_dt()
1007 clk = devm_clk_get(dsi->dev, "phy_ref"); in nwl_dsi_parse_dt()
1010 DRM_DEV_ERROR(dsi->dev, "Failed to get phy_ref clock: %d\n", in nwl_dsi_parse_dt()
1014 dsi->phy_ref_clk = clk; in nwl_dsi_parse_dt()
1016 clk = devm_clk_get(dsi->dev, "rx_esc"); in nwl_dsi_parse_dt()
1019 DRM_DEV_ERROR(dsi->dev, "Failed to get rx_esc clock: %d\n", in nwl_dsi_parse_dt()
1023 dsi->rx_esc_clk = clk; in nwl_dsi_parse_dt()
1025 clk = devm_clk_get(dsi->dev, "tx_esc"); in nwl_dsi_parse_dt()
1028 DRM_DEV_ERROR(dsi->dev, "Failed to get tx_esc clock: %d\n", in nwl_dsi_parse_dt()
1032 dsi->tx_esc_clk = clk; in nwl_dsi_parse_dt()
1034 dsi->mux = devm_mux_control_get(dsi->dev, NULL); in nwl_dsi_parse_dt()
1035 if (IS_ERR(dsi->mux)) { in nwl_dsi_parse_dt()
1036 ret = PTR_ERR(dsi->mux); in nwl_dsi_parse_dt()
1038 DRM_DEV_ERROR(dsi->dev, "Failed to get mux: %d\n", ret); in nwl_dsi_parse_dt()
1046 dsi->regmap = in nwl_dsi_parse_dt()
1047 devm_regmap_init_mmio(dsi->dev, base, &nwl_dsi_regmap_config); in nwl_dsi_parse_dt()
1048 if (IS_ERR(dsi->regmap)) { in nwl_dsi_parse_dt()
1049 ret = PTR_ERR(dsi->regmap); in nwl_dsi_parse_dt()
1050 DRM_DEV_ERROR(dsi->dev, "Failed to create NWL DSI regmap: %d\n", in nwl_dsi_parse_dt()
1055 dsi->irq = platform_get_irq(pdev, 0); in nwl_dsi_parse_dt()
1056 if (dsi->irq < 0) { in nwl_dsi_parse_dt()
1057 DRM_DEV_ERROR(dsi->dev, "Failed to get device IRQ: %d\n", in nwl_dsi_parse_dt()
1058 dsi->irq); in nwl_dsi_parse_dt()
1059 return dsi->irq; in nwl_dsi_parse_dt()
1062 dsi->rst_pclk = devm_reset_control_get_exclusive(dsi->dev, "pclk"); in nwl_dsi_parse_dt()
1063 if (IS_ERR(dsi->rst_pclk)) { in nwl_dsi_parse_dt()
1064 DRM_DEV_ERROR(dsi->dev, "Failed to get pclk reset: %ld\n", in nwl_dsi_parse_dt()
1065 PTR_ERR(dsi->rst_pclk)); in nwl_dsi_parse_dt()
1066 return PTR_ERR(dsi->rst_pclk); in nwl_dsi_parse_dt()
1068 dsi->rst_byte = devm_reset_control_get_exclusive(dsi->dev, "byte"); in nwl_dsi_parse_dt()
1069 if (IS_ERR(dsi->rst_byte)) { in nwl_dsi_parse_dt()
1070 DRM_DEV_ERROR(dsi->dev, "Failed to get byte reset: %ld\n", in nwl_dsi_parse_dt()
1071 PTR_ERR(dsi->rst_byte)); in nwl_dsi_parse_dt()
1072 return PTR_ERR(dsi->rst_byte); in nwl_dsi_parse_dt()
1074 dsi->rst_esc = devm_reset_control_get_exclusive(dsi->dev, "esc"); in nwl_dsi_parse_dt()
1075 if (IS_ERR(dsi->rst_esc)) { in nwl_dsi_parse_dt()
1076 DRM_DEV_ERROR(dsi->dev, "Failed to get esc reset: %ld\n", in nwl_dsi_parse_dt()
1077 PTR_ERR(dsi->rst_esc)); in nwl_dsi_parse_dt()
1078 return PTR_ERR(dsi->rst_esc); in nwl_dsi_parse_dt()
1080 dsi->rst_dpi = devm_reset_control_get_exclusive(dsi->dev, "dpi"); in nwl_dsi_parse_dt()
1081 if (IS_ERR(dsi->rst_dpi)) { in nwl_dsi_parse_dt()
1082 DRM_DEV_ERROR(dsi->dev, "Failed to get dpi reset: %ld\n", in nwl_dsi_parse_dt()
1083 PTR_ERR(dsi->rst_dpi)); in nwl_dsi_parse_dt()
1084 return PTR_ERR(dsi->rst_dpi); in nwl_dsi_parse_dt()
1089 static int nwl_dsi_select_input(struct nwl_dsi *dsi) in nwl_dsi_select_input() argument
1095 remote = of_graph_get_remote_node(dsi->dev->of_node, 0, in nwl_dsi_select_input()
1100 remote = of_graph_get_remote_node(dsi->dev->of_node, 0, in nwl_dsi_select_input()
1103 DRM_DEV_ERROR(dsi->dev, in nwl_dsi_select_input()
1109 DRM_DEV_INFO(dsi->dev, "Using %s as input source\n", in nwl_dsi_select_input()
1111 ret = mux_control_try_select(dsi->mux, use_dcss); in nwl_dsi_select_input()
1113 DRM_DEV_ERROR(dsi->dev, "Failed to select input: %d\n", ret); in nwl_dsi_select_input()
1119 static int nwl_dsi_deselect_input(struct nwl_dsi *dsi) in nwl_dsi_deselect_input() argument
1123 ret = mux_control_deselect(dsi->mux); in nwl_dsi_deselect_input()
1125 DRM_DEV_ERROR(dsi->dev, "Failed to deselect input: %d\n", ret); in nwl_dsi_deselect_input()
1135 { .compatible = "fsl,imx8mq-nwl-dsi", },
1150 struct nwl_dsi *dsi; in nwl_dsi_probe() local
1153 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); in nwl_dsi_probe()
1154 if (!dsi) in nwl_dsi_probe()
1157 dsi->dev = dev; in nwl_dsi_probe()
1159 ret = nwl_dsi_parse_dt(dsi); in nwl_dsi_probe()
1163 ret = devm_request_irq(dev, dsi->irq, nwl_dsi_irq_handler, 0, in nwl_dsi_probe()
1164 dev_name(dev), dsi); in nwl_dsi_probe()
1166 DRM_DEV_ERROR(dev, "Failed to request IRQ %d: %d\n", dsi->irq, in nwl_dsi_probe()
1171 dsi->dsi_host.ops = &nwl_dsi_host_ops; in nwl_dsi_probe()
1172 dsi->dsi_host.dev = dev; in nwl_dsi_probe()
1173 ret = mipi_dsi_host_register(&dsi->dsi_host); in nwl_dsi_probe()
1181 dsi->quirks = (uintptr_t)attr->data; in nwl_dsi_probe()
1183 dsi->bridge.driver_private = dsi; in nwl_dsi_probe()
1184 dsi->bridge.funcs = &nwl_dsi_bridge_funcs; in nwl_dsi_probe()
1185 dsi->bridge.of_node = dev->of_node; in nwl_dsi_probe()
1186 dsi->bridge.timings = &nwl_dsi_timings; in nwl_dsi_probe()
1188 dev_set_drvdata(dev, dsi); in nwl_dsi_probe()
1191 ret = nwl_dsi_select_input(dsi); in nwl_dsi_probe()
1194 mipi_dsi_host_unregister(&dsi->dsi_host); in nwl_dsi_probe()
1198 drm_bridge_add(&dsi->bridge); in nwl_dsi_probe()
1204 struct nwl_dsi *dsi = platform_get_drvdata(pdev); in nwl_dsi_remove() local
1206 nwl_dsi_deselect_input(dsi); in nwl_dsi_remove()
1207 mipi_dsi_host_unregister(&dsi->dsi_host); in nwl_dsi_remove()
1208 drm_bridge_remove(&dsi->bridge); in nwl_dsi_remove()
1226 MODULE_DESCRIPTION("Northwest Logic MIPI-DSI driver");