1 // SPDX-License-Identifier: GPL-2.0+
16 #include <linux/gpio/consumer.h>
18 #include <linux/media-bus-format.h>
214 	return ret == val_size ? 0 : -EINVAL;  in chipone_dsi_read()
240 	ret = regmap_read(icn->regmap, reg, &pval);  in chipone_readb()
247 	return regmap_write(icn->regmap, reg, val);  in chipone_writeb()
254 	unsigned int mode_clock = mode->clock * 1000;  in chipone_configure_pll()
271 	 * P is pre-divider, register PLL_REF_DIV[3:0] is 1:n divider  in chipone_configure_pll()
274 	 * S is post-divider, register PLL_REF_DIV[7:5] is 2^(n+1) divider  in chipone_configure_pll()
276 	 * It seems the PLL input clock after applying P pre-divider have  in chipone_configure_pll()
279 	if (icn->refclk)  in chipone_configure_pll()
280 		fin = icn->refclk_rate;  in chipone_configure_pll()
282 		fin = icn->dsi->hs_rate / 4; /* in Hz */  in chipone_configure_pll()
311 			/* Apply post-divider */  in chipone_configure_pll()
314 			delta = abs(mode_clock - freq_out);  in chipone_configure_pll()
326 	dev_dbg(icn->dev,  in chipone_configure_pll()
329 		min_delta, icn->refclk ? "EXT" : "DSI", fin,  in chipone_configure_pll()
333 	if (best_p_pot)	/* Prefer /2 pre-divider */  in chipone_configure_pll()
338 		       icn->refclk ? PLL_CTRL_6_EXTERNAL : PLL_CTRL_6_MIPI_CLK);  in chipone_configure_pll()
347 	struct drm_atomic_state *state = old_bridge_state->base.state;  in chipone_atomic_enable()
348 	struct drm_display_mode *mode = &icn->mode;  in chipone_atomic_enable()
352 	u8 pol, sys_ctrl_1, id[4];  in chipone_atomic_enable()  local
359 	dev_dbg(icn->dev,  in chipone_atomic_enable()
364 		dev_dbg(icn->dev, "Invalid Chip IDs, aborting configuration\n");  in chipone_atomic_enable()
370 	bus_flags = bridge_state->output_bus_cfg.flags;  in chipone_atomic_enable()
372 	if (icn->interface_i2c)  in chipone_atomic_enable()
377 	chipone_writeb(icn, HACTIVE_LI, mode->hdisplay & 0xff);  in chipone_atomic_enable()
379 	chipone_writeb(icn, VACTIVE_LI, mode->vdisplay & 0xff);  in chipone_atomic_enable()
386 		       ((mode->hdisplay >> 8) & 0xf) |  in chipone_atomic_enable()
387 		       (((mode->vdisplay >> 8) & 0xf) << 4));  in chipone_atomic_enable()
389 	hfp = mode->hsync_start - mode->hdisplay;  in chipone_atomic_enable()
390 	hsync = mode->hsync_end - mode->hsync_start;  in chipone_atomic_enable()
391 	hbp = mode->htotal - mode->hsync_end;  in chipone_atomic_enable()
402 	chipone_writeb(icn, VFP, mode->vsync_start - mode->vdisplay);  in chipone_atomic_enable()
404 	chipone_writeb(icn, VSYNC, mode->vsync_end - mode->vsync_start);  in chipone_atomic_enable()
406 	chipone_writeb(icn, VBP, mode->vtotal - mode->vsync_end);  in chipone_atomic_enable()
414 		       DSI_CTRL_UNKNOWN | DSI_CTRL_DSI_LANES(icn->dsi->lanes - 1));  in chipone_atomic_enable()
421 	pol = ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIST_POL_HSYNC_POL : 0) |  in chipone_atomic_enable()
422 	      ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIST_POL_VSYNC_POL : 0) |  in chipone_atomic_enable()
424 	chipone_writeb(icn, BIST_POL, pol);  in chipone_atomic_enable()
453 	if (icn->vdd1) {  in chipone_atomic_pre_enable()
454 		ret = regulator_enable(icn->vdd1);  in chipone_atomic_pre_enable()
456 			DRM_DEV_ERROR(icn->dev,  in chipone_atomic_pre_enable()
460 	if (icn->vdd2) {  in chipone_atomic_pre_enable()
461 		ret = regulator_enable(icn->vdd2);  in chipone_atomic_pre_enable()
463 			DRM_DEV_ERROR(icn->dev,  in chipone_atomic_pre_enable()
467 	if (icn->vdd3) {  in chipone_atomic_pre_enable()
468 		ret = regulator_enable(icn->vdd3);  in chipone_atomic_pre_enable()
470 			DRM_DEV_ERROR(icn->dev,  in chipone_atomic_pre_enable()
474 	ret = clk_prepare_enable(icn->refclk);  in chipone_atomic_pre_enable()
476 		DRM_DEV_ERROR(icn->dev,  in chipone_atomic_pre_enable()
479 	gpiod_set_value(icn->enable_gpio, 1);  in chipone_atomic_pre_enable()
489 	clk_disable_unprepare(icn->refclk);  in chipone_atomic_post_disable()
491 	if (icn->vdd1)  in chipone_atomic_post_disable()
492 		regulator_disable(icn->vdd1);  in chipone_atomic_post_disable()
494 	if (icn->vdd2)  in chipone_atomic_post_disable()
495 		regulator_disable(icn->vdd2);  in chipone_atomic_post_disable()
497 	if (icn->vdd3)  in chipone_atomic_post_disable()
498 		regulator_disable(icn->vdd3);  in chipone_atomic_post_disable()
500 	gpiod_set_value(icn->enable_gpio, 0);  in chipone_atomic_post_disable()
509 	drm_mode_copy(&icn->mode, adjusted_mode);  in chipone_mode_set()
514 	struct mipi_dsi_device *dsi = icn->dsi;  in chipone_dsi_attach()
515 	struct device *dev = icn->dev;  in chipone_dsi_attach()
518 	dsi_lanes = drm_of_get_data_lanes_count_ep(dev->of_node, 0, 0, 1, 4);  in chipone_dsi_attach()
521 	 * If the 'data-lanes' property does not exist in DT or is invalid,  in chipone_dsi_attach()
522 	 * default to previously hard-coded behavior, which was 4 data lanes.  in chipone_dsi_attach()
525 		icn->dsi->lanes = 4;  in chipone_dsi_attach()
527 		icn->dsi->lanes = dsi_lanes;  in chipone_dsi_attach()
529 	dsi->format = MIPI_DSI_FMT_RGB888;  in chipone_dsi_attach()
530 	dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |  in chipone_dsi_attach()
532 	dsi->hs_rate = 500000000;  in chipone_dsi_attach()
533 	dsi->lp_rate = 16000000;  in chipone_dsi_attach()
537 		dev_err(icn->dev, "failed to attach dsi\n");  in chipone_dsi_attach()
544 	struct device *dev = icn->dev;  in chipone_dsi_host_attach()
557 	endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0);  in chipone_dsi_host_attach()
562 		return -EINVAL;  in chipone_dsi_host_attach()
568 		return -EPROBE_DEFER;  in chipone_dsi_host_attach()
577 	icn->dsi = dsi;  in chipone_dsi_host_attach()
590 	return drm_bridge_attach(bridge->encoder, icn->panel_bridge, bridge, flags);  in chipone_attach()
612 	/* This is the DSI-end bus format */  in chipone_atomic_get_input_bus_fmts()
633 	struct device *dev = icn->dev;  in chipone_parse_dt()
636 	icn->refclk = devm_clk_get_optional(dev, "refclk");  in chipone_parse_dt()
637 	if (IS_ERR(icn->refclk)) {  in chipone_parse_dt()
638 		ret = PTR_ERR(icn->refclk);  in chipone_parse_dt()
641 	} else if (icn->refclk) {  in chipone_parse_dt()
642 		icn->refclk_rate = clk_get_rate(icn->refclk);  in chipone_parse_dt()
643 		if (icn->refclk_rate < 10000000 || icn->refclk_rate > 154000000) {  in chipone_parse_dt()
644 			DRM_DEV_ERROR(dev, "REFCLK out of range: %ld Hz\n",  in chipone_parse_dt()
645 				      icn->refclk_rate);  in chipone_parse_dt()
646 			return -EINVAL;  in chipone_parse_dt()
650 	icn->vdd1 = devm_regulator_get_optional(dev, "vdd1");  in chipone_parse_dt()
651 	if (IS_ERR(icn->vdd1)) {  in chipone_parse_dt()
652 		ret = PTR_ERR(icn->vdd1);  in chipone_parse_dt()
653 		if (ret == -EPROBE_DEFER)  in chipone_parse_dt()
654 			return -EPROBE_DEFER;  in chipone_parse_dt()
655 		icn->vdd1 = NULL;  in chipone_parse_dt()
659 	icn->vdd2 = devm_regulator_get_optional(dev, "vdd2");  in chipone_parse_dt()
660 	if (IS_ERR(icn->vdd2)) {  in chipone_parse_dt()
661 		ret = PTR_ERR(icn->vdd2);  in chipone_parse_dt()
662 		if (ret == -EPROBE_DEFER)  in chipone_parse_dt()
663 			return -EPROBE_DEFER;  in chipone_parse_dt()
664 		icn->vdd2 = NULL;  in chipone_parse_dt()
668 	icn->vdd3 = devm_regulator_get_optional(dev, "vdd3");  in chipone_parse_dt()
669 	if (IS_ERR(icn->vdd3)) {  in chipone_parse_dt()
670 		ret = PTR_ERR(icn->vdd3);  in chipone_parse_dt()
671 		if (ret == -EPROBE_DEFER)  in chipone_parse_dt()
672 			return -EPROBE_DEFER;  in chipone_parse_dt()
673 		icn->vdd3 = NULL;  in chipone_parse_dt()
677 	icn->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);  in chipone_parse_dt()
678 	if (IS_ERR(icn->enable_gpio)) {  in chipone_parse_dt()
679 		DRM_DEV_ERROR(dev, "failed to get enable GPIO\n");  in chipone_parse_dt()
680 		return PTR_ERR(icn->enable_gpio);  in chipone_parse_dt()
683 	icn->panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);  in chipone_parse_dt()
684 	if (IS_ERR(icn->panel_bridge))  in chipone_parse_dt()
685 		return PTR_ERR(icn->panel_bridge);  in chipone_parse_dt()
697 		return -ENOMEM;  in chipone_common_probe()
699 	icn->dev = dev;  in chipone_common_probe()
705 	icn->bridge.funcs = &chipone_bridge_funcs;  in chipone_common_probe()
706 	icn->bridge.type = DRM_MODE_CONNECTOR_DPI;  in chipone_common_probe()
707 	icn->bridge.of_node = dev->of_node;  in chipone_common_probe()
716 	struct device *dev = &dsi->dev;  in chipone_dsi_probe()
724 	icn->regmap = devm_regmap_init(dev, &chipone_dsi_regmap_bus,  in chipone_dsi_probe()
726 	if (IS_ERR(icn->regmap))  in chipone_dsi_probe()
727 		return PTR_ERR(icn->regmap);  in chipone_dsi_probe()
729 	icn->interface_i2c = false;  in chipone_dsi_probe()
730 	icn->dsi = dsi;  in chipone_dsi_probe()
734 	drm_bridge_add(&icn->bridge);  in chipone_dsi_probe()
738 		drm_bridge_remove(&icn->bridge);  in chipone_dsi_probe()
746 	struct device *dev = &client->dev;  in chipone_i2c_probe()
754 	icn->regmap = devm_regmap_init_i2c(client, &chipone_regmap_config);  in chipone_i2c_probe()
755 	if (IS_ERR(icn->regmap))  in chipone_i2c_probe()
756 		return PTR_ERR(icn->regmap);  in chipone_i2c_probe()
758 	icn->interface_i2c = true;  in chipone_i2c_probe()
759 	icn->client = client;  in chipone_i2c_probe()
763 	drm_bridge_add(&icn->bridge);  in chipone_i2c_probe()
773 	drm_bridge_remove(&icn->bridge);  in chipone_dsi_remove()
786 		.name = "chipone-icn6211",
802 		.name = "chipone-icn6211-i2c",
826 MODULE_DESCRIPTION("Chipone ICN6211 MIPI-DSI to RGB Converter Bridge");