Lines Matching +full:24 +full:gbit

252 		ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));  in cbrdlli_ast2150()
269 	ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));  in cbrdlli_ast2150()
629 		ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));  in finetuneDQI_L()
748 				ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));  in finetuneDQSI()
821 		ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));  in cbr_dll2()
1781 	/* Check 8Gbit */  in check_dram_size_2500()
1784 		reg_14 |= (tRFC >> 24) & 0xFF;  in check_dram_size_2500()
1785 		/* Check 4Gbit */  in check_dram_size_2500()
1789 		/* Check 2Gbit */  in check_dram_size_2500()
1833 		/* CLKIN = 24MHz */  in set_mpll_2500()
2090 		 *	[23]:= 1:CLKIN is 25MHz and USBCK1 = 24/48 MHz (determined by  in ast_post_chip_2500()
2091 		 *				[18]: 0(24)/1(48) MHz)  in ast_post_chip_2500()