Lines Matching +full:0 +full:xdc
13 u8 i = 0, j = 0; in ast_astdp_read_edid()
21 if (!(ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD1, ASTDP_MCU_FW_EXECUTING) && in ast_astdp_read_edid()
22 ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDC, ASTDP_LINK_SUCCESS) && in ast_astdp_read_edid()
23 ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDF, ASTDP_HPD) && in ast_astdp_read_edid()
24 ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5, in ast_astdp_read_edid()
29 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5, (u8) ~ASTDP_HOST_EDID_READ_DONE_MASK, in ast_astdp_read_edid()
30 0x00); in ast_astdp_read_edid()
32 for (i = 0; i < 32; i++) { in ast_astdp_read_edid()
34 * CRE4[7:0]: Read-Pointer for EDID (Unit: 4bytes); valid range: 0~64 in ast_astdp_read_edid()
36 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE4, in ast_astdp_read_edid()
38 j = 0; in ast_astdp_read_edid()
44 while ((ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD7, in ast_astdp_read_edid()
45 ASTDP_EDID_VALID_FLAG_MASK) != 0x01) || in ast_astdp_read_edid()
46 (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD6, in ast_astdp_read_edid()
56 if (!(ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD1, in ast_astdp_read_edid()
58 ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDC, in ast_astdp_read_edid()
60 ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDF, ASTDP_HPD))) { in ast_astdp_read_edid()
70 0xD8, ASTDP_EDID_READ_DATA_MASK); in ast_astdp_read_edid()
71 *(ediddata + 1) = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD9, in ast_astdp_read_edid()
73 *(ediddata + 2) = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDA, in ast_astdp_read_edid()
75 *(ediddata + 3) = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDB, in ast_astdp_read_edid()
83 * equal 0 (mod 256). in ast_astdp_read_edid()
84 * 2. Modify Bytes-126 to be 0. in ast_astdp_read_edid()
86 * follow. 0 represents noextensions. in ast_astdp_read_edid()
89 *(ediddata + 2) = 0; in ast_astdp_read_edid()
95 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5, (u8) ~ASTDP_HOST_EDID_READ_DONE_MASK, in ast_astdp_read_edid()
98 return 0; in ast_astdp_read_edid()
101 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5, in ast_astdp_read_edid()
107 if (!(ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD1, ASTDP_MCU_FW_EXECUTING))) in ast_astdp_read_edid()
108 return (~0xD1 + 1); in ast_astdp_read_edid()
109 if (!(ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDC, ASTDP_LINK_SUCCESS))) in ast_astdp_read_edid()
110 return (~0xDC + 1); in ast_astdp_read_edid()
111 if (!(ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDF, ASTDP_HPD))) in ast_astdp_read_edid()
112 return (~0xDF + 1); in ast_astdp_read_edid()
113 if (!(ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5, ASTDP_HOST_EDID_READ_DONE_MASK))) in ast_astdp_read_edid()
114 return (~0xE5 + 1); in ast_astdp_read_edid()
116 return 0; in ast_astdp_read_edid()
124 u32 i = 0, j = 0, WaitCount = 1; in ast_dp_launch()
125 u8 bDPTX = 0; in ast_dp_launch()
135 for (j = 0; j < WaitCount; j++) { in ast_dp_launch()
136 bDPTX = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD1, TX_TYPE_MASK); in ast_dp_launch()
144 // 0xE : ASTDP with DPMCU FW handling in ast_dp_launch()
147 i = 0; in ast_dp_launch()
149 while (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD1, COPROCESSOR_LAUNCH) != in ast_dp_launch()
157 bDPExecute = 0; in ast_dp_launch()
165 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5, in ast_dp_launch()
177 u8 bE3 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE3, AST_DP_VIDEO_ENABLE); in ast_dp_power_on_off()
184 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE3, (u8) ~AST_DP_PHY_SLEEP, bE3); in ast_dp_power_on_off()
195 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE3, (u8) ~AST_DP_VIDEO_ENABLE, on); in ast_dp_set_on_off()
198 if (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDC, ASTDP_LINK_SUCCESS) && in ast_dp_set_on_off()
199 ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDF, ASTDP_HPD)) { in ast_dp_set_on_off()
201 while (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDF, in ast_dp_set_on_off()
273 * CRE0[7:0]: MISC0 ((0x00: 18-bpp) or (0x20: 24-bpp) in ast_dp_set_mode()
274 * CRE1[7:0]: MISC1 (default: 0x00) in ast_dp_set_mode()
275 * CRE2[7:0]: video format index (0x00 ~ 0x20 or 0x40 ~ 0x50) in ast_dp_set_mode()
277 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE0, ASTDP_AND_CLEAR_MASK, in ast_dp_set_mode()
279 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE1, ASTDP_AND_CLEAR_MASK, ASTDP_MISC1); in ast_dp_set_mode()
280 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE2, ASTDP_AND_CLEAR_MASK, ModeIdx); in ast_dp_set_mode()