Lines Matching +full:0 +full:x22
29 #define MC_CG_CONFIG 0x96f
30 #define MC_ARB_CG 0x9fa
31 #define CG_ARB_REQ(x) ((x) << 0)
32 #define CG_ARB_REQ_MASK (0xff << 0)
34 #define MC_ARB_DRAM_TIMING_1 0x9fc
35 #define MC_ARB_DRAM_TIMING_2 0x9fd
36 #define MC_ARB_DRAM_TIMING_3 0x9fe
37 #define MC_ARB_DRAM_TIMING2_1 0x9ff
38 #define MC_ARB_DRAM_TIMING2_2 0xa00
39 #define MC_ARB_DRAM_TIMING2_3 0xa01
56 #define RV770_SMC_TABLE_ADDRESS 0xB000
59 #define SMC_STROBE_RATIO 0x0F
60 #define SMC_STROBE_ENABLE 0x10
62 #define SMC_MC_EDC_RD_FLAG 0x01
63 #define SMC_MC_EDC_WR_FLAG 0x02
64 #define SMC_MC_RTT_ENABLE 0x04
65 #define SMC_MC_STUTTER_EN 0x08
67 #define RV770_SMC_VOLTAGEMASK_VDDC 0
73 #define NISLANDS_SMC_STROBE_RATIO 0x0F
74 #define NISLANDS_SMC_STROBE_ENABLE 0x10
76 #define NISLANDS_SMC_MC_EDC_RD_FLAG 0x01
77 #define NISLANDS_SMC_MC_EDC_WR_FLAG 0x02
78 #define NISLANDS_SMC_MC_RTT_ENABLE 0x04
79 #define NISLANDS_SMC_MC_STUTTER_EN 0x08
83 #define NISLANDS_SMC_VOLTAGEMASK_VDDC 0
88 #define SISLANDS_MCREGISTERTABLE_INITIAL_SLOT 0
93 #define SISLANDS_LEAKAGE_INDEX0 0xff01
97 #define SISLANDS_INITIAL_STATE_ARB_INDEX 0
113 #define SISLANDS_DPM2_SQ_RAMP_MAX_POWER 0x3FFF
114 #define SISLANDS_DPM2_SQ_RAMP_MIN_POWER 0x12
115 #define SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15
116 #define SISLANDS_DPM2_SQ_RAMP_STI_SIZE 0x1E
117 #define SISLANDS_DPM2_SQ_RAMP_LTI_RATIO 0xF
121 #define SISLANDS_VRC_DFLT 0xC000B3
123 #define SISLANDS_CGULVPARAMETER_DFLT 0x00040035
124 #define SISLANDS_CGULVCONTROL_DFLT 0x1f007550
127 #define SI_BSP_DFLT 0x41EB
128 #define SI_BSU_DFLT 0x2
134 #define SI_TD_DFLT 0
135 #define SI_UTC_DFLT_00 0x24
136 #define SI_UTC_DFLT_01 0x22
137 #define SI_UTC_DFLT_02 0x22
138 #define SI_UTC_DFLT_03 0x22
139 #define SI_UTC_DFLT_04 0x22
140 #define SI_UTC_DFLT_05 0x22
141 #define SI_UTC_DFLT_06 0x22
142 #define SI_UTC_DFLT_07 0x22
143 #define SI_UTC_DFLT_08 0x22
144 #define SI_UTC_DFLT_09 0x22
145 #define SI_UTC_DFLT_10 0x22
146 #define SI_UTC_DFLT_11 0x22
147 #define SI_UTC_DFLT_12 0x22
148 #define SI_UTC_DFLT_13 0x22
149 #define SI_UTC_DFLT_14 0x22
150 #define SI_DTC_DFLT_00 0x24
151 #define SI_DTC_DFLT_01 0x22
152 #define SI_DTC_DFLT_02 0x22
153 #define SI_DTC_DFLT_03 0x22
154 #define SI_DTC_DFLT_04 0x22
155 #define SI_DTC_DFLT_05 0x22
156 #define SI_DTC_DFLT_06 0x22
157 #define SI_DTC_DFLT_07 0x22
158 #define SI_DTC_DFLT_08 0x22
159 #define SI_DTC_DFLT_09 0x22
160 #define SI_DTC_DFLT_10 0x22
161 #define SI_DTC_DFLT_11 0x22
162 #define SI_DTC_DFLT_12 0x22
163 #define SI_DTC_DFLT_13 0x22
164 #define SI_DTC_DFLT_14 0x22
165 #define SI_VRC_DFLT 0x0000C003
168 #define SI_VRU_DFLT 0x3
169 #define SI_SPLLSTEPTIME_DFLT 0x1000
170 #define SI_SPLLSTEPUNIT_DFLT 0x3
171 #define SI_TPU_DFLT 0
172 #define SI_TPC_DFLT 0x200
173 #define SI_SSTU_DFLT 0
174 #define SI_SST_DFLT 0x00C8
175 #define SI_GICST_DFLT 0x200
176 #define SI_FCT_DFLT 0x0400
177 #define SI_FCTU_DFLT 0
178 #define SI_CTXCGTT3DRPHC_DFLT 0x20
179 #define SI_CTXCGTT3DRSDC_DFLT 0x40
180 #define SI_VDDC3DOORPHC_DFLT 0x100
181 #define SI_VDDC3DOORSDC_DFLT 0x7
182 #define SI_VDDC3DOORSU_DFLT 0
204 NISLANDS_DCCAC_LEVEL_0 = 0,
217 SISLANDS_CACCONFIG_MMR = 0,
223 SI_POWER_LEVEL_LOW = 0,
236 SI_DISPLAY_WATERMARK_LOW = 0,
242 SI_PM_DISPLAY_GAP_VBLANK_OR_WM = 0,
599 SI_PCIE_GEN1 = 0,
602 SI_PCIE_GEN_INVALID = 0xffff