Lines Matching refs:adev
36 #define amdgpu_dpm_enable_bapm(adev, e) \ argument
37 ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))
39 int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) in amdgpu_dpm_get_sclk() argument
41 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_sclk()
47 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_sclk()
48 ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, in amdgpu_dpm_get_sclk()
50 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_sclk()
55 int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) in amdgpu_dpm_get_mclk() argument
57 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_mclk()
63 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_mclk()
64 ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle, in amdgpu_dpm_get_mclk()
66 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_mclk()
71 int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block_type, bool gate) in amdgpu_dpm_set_powergating_by_smu() argument
74 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_powergating_by_smu()
77 if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state) { in amdgpu_dpm_set_powergating_by_smu()
78 dev_dbg(adev->dev, "IP block%d already in the target %s state!", in amdgpu_dpm_set_powergating_by_smu()
83 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_powergating_by_smu()
96 (adev)->powerplay.pp_handle, block_type, gate)); in amdgpu_dpm_set_powergating_by_smu()
103 atomic_set(&adev->pm.pwr_state[block_type], pwr_state); in amdgpu_dpm_set_powergating_by_smu()
105 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_powergating_by_smu()
110 int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev) in amdgpu_dpm_set_gfx_power_up_by_imu() argument
112 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_set_gfx_power_up_by_imu()
115 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_gfx_power_up_by_imu()
117 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_gfx_power_up_by_imu()
124 int amdgpu_dpm_baco_enter(struct amdgpu_device *adev) in amdgpu_dpm_baco_enter() argument
126 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_baco_enter()
127 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_baco_enter()
133 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_baco_enter()
138 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_baco_enter()
143 int amdgpu_dpm_baco_exit(struct amdgpu_device *adev) in amdgpu_dpm_baco_exit() argument
145 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_baco_exit()
146 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_baco_exit()
152 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_baco_exit()
157 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_baco_exit()
162 int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, in amdgpu_dpm_set_mp1_state() argument
166 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_mp1_state()
169 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_mp1_state()
172 adev->powerplay.pp_handle, in amdgpu_dpm_set_mp1_state()
175 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_mp1_state()
181 bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) in amdgpu_dpm_is_baco_supported() argument
183 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_is_baco_supported()
184 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_is_baco_supported()
199 if (adev->in_s3) in amdgpu_dpm_is_baco_supported()
202 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_is_baco_supported()
207 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_is_baco_supported()
212 int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) in amdgpu_dpm_mode2_reset() argument
214 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_mode2_reset()
215 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_mode2_reset()
221 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_mode2_reset()
225 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_mode2_reset()
230 int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) in amdgpu_dpm_baco_reset() argument
232 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_baco_reset()
233 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_baco_reset()
239 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_baco_reset()
250 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_baco_reset()
254 bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) in amdgpu_dpm_is_mode1_reset_supported() argument
256 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_is_mode1_reset_supported()
259 if (is_support_sw_smu(adev)) { in amdgpu_dpm_is_mode1_reset_supported()
260 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_is_mode1_reset_supported()
262 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_is_mode1_reset_supported()
268 int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev) in amdgpu_dpm_mode1_reset() argument
270 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_mode1_reset()
273 if (is_support_sw_smu(adev)) { in amdgpu_dpm_mode1_reset()
274 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_mode1_reset()
276 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_mode1_reset()
282 int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, in amdgpu_dpm_switch_power_profile() argument
286 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_switch_power_profile()
289 if (amdgpu_sriov_vf(adev)) in amdgpu_dpm_switch_power_profile()
293 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_switch_power_profile()
295 adev->powerplay.pp_handle, type, en); in amdgpu_dpm_switch_power_profile()
296 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_switch_power_profile()
302 int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, in amdgpu_dpm_set_xgmi_pstate() argument
305 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_xgmi_pstate()
309 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_xgmi_pstate()
310 ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, in amdgpu_dpm_set_xgmi_pstate()
312 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_xgmi_pstate()
318 int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, in amdgpu_dpm_set_df_cstate() argument
322 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_df_cstate()
323 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_set_df_cstate()
326 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_df_cstate()
328 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_df_cstate()
334 int amdgpu_dpm_allow_xgmi_power_down(struct amdgpu_device *adev, bool en) in amdgpu_dpm_allow_xgmi_power_down() argument
336 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_allow_xgmi_power_down()
339 if (is_support_sw_smu(adev)) { in amdgpu_dpm_allow_xgmi_power_down()
340 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_allow_xgmi_power_down()
342 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_allow_xgmi_power_down()
348 int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) in amdgpu_dpm_enable_mgpu_fan_boost() argument
350 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_enable_mgpu_fan_boost()
352 adev->powerplay.pp_funcs; in amdgpu_dpm_enable_mgpu_fan_boost()
356 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_enable_mgpu_fan_boost()
358 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_enable_mgpu_fan_boost()
364 int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, in amdgpu_dpm_set_clockgating_by_smu() argument
367 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_set_clockgating_by_smu()
369 adev->powerplay.pp_funcs; in amdgpu_dpm_set_clockgating_by_smu()
373 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_clockgating_by_smu()
376 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_clockgating_by_smu()
382 int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, in amdgpu_dpm_smu_i2c_bus_access() argument
385 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_smu_i2c_bus_access()
387 adev->powerplay.pp_funcs; in amdgpu_dpm_smu_i2c_bus_access()
391 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_smu_i2c_bus_access()
394 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_smu_i2c_bus_access()
400 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) in amdgpu_pm_acpi_event_handler() argument
402 if (adev->pm.dpm_enabled) { in amdgpu_pm_acpi_event_handler()
403 mutex_lock(&adev->pm.mutex); in amdgpu_pm_acpi_event_handler()
405 adev->pm.ac_power = true; in amdgpu_pm_acpi_event_handler()
407 adev->pm.ac_power = false; in amdgpu_pm_acpi_event_handler()
409 if (adev->powerplay.pp_funcs && in amdgpu_pm_acpi_event_handler()
410 adev->powerplay.pp_funcs->enable_bapm) in amdgpu_pm_acpi_event_handler()
411 amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); in amdgpu_pm_acpi_event_handler()
413 if (is_support_sw_smu(adev)) in amdgpu_pm_acpi_event_handler()
414 smu_set_ac_dc(adev->powerplay.pp_handle); in amdgpu_pm_acpi_event_handler()
416 mutex_unlock(&adev->pm.mutex); in amdgpu_pm_acpi_event_handler()
420 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, in amdgpu_dpm_read_sensor() argument
423 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_read_sensor()
430 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_read_sensor()
431 ret = pp_funcs->read_sensor(adev->powerplay.pp_handle, in amdgpu_dpm_read_sensor()
435 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_read_sensor()
441 void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) in amdgpu_dpm_compute_clocks() argument
443 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_compute_clocks()
446 if (!adev->pm.dpm_enabled) in amdgpu_dpm_compute_clocks()
452 if (adev->mode_info.num_crtc) in amdgpu_dpm_compute_clocks()
453 amdgpu_display_bandwidth_update(adev); in amdgpu_dpm_compute_clocks()
456 struct amdgpu_ring *ring = adev->rings[i]; in amdgpu_dpm_compute_clocks()
461 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_compute_clocks()
462 pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle); in amdgpu_dpm_compute_clocks()
463 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_compute_clocks()
466 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) in amdgpu_dpm_enable_uvd() argument
470 if (adev->family == AMDGPU_FAMILY_SI) { in amdgpu_dpm_enable_uvd()
471 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_enable_uvd()
473 adev->pm.dpm.uvd_active = true; in amdgpu_dpm_enable_uvd()
474 adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; in amdgpu_dpm_enable_uvd()
476 adev->pm.dpm.uvd_active = false; in amdgpu_dpm_enable_uvd()
478 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_enable_uvd()
480 amdgpu_dpm_compute_clocks(adev); in amdgpu_dpm_enable_uvd()
484 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable); in amdgpu_dpm_enable_uvd()
490 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) in amdgpu_dpm_enable_vce() argument
494 if (adev->family == AMDGPU_FAMILY_SI) { in amdgpu_dpm_enable_vce()
495 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_enable_vce()
497 adev->pm.dpm.vce_active = true; in amdgpu_dpm_enable_vce()
499 adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; in amdgpu_dpm_enable_vce()
501 adev->pm.dpm.vce_active = false; in amdgpu_dpm_enable_vce()
503 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_enable_vce()
505 amdgpu_dpm_compute_clocks(adev); in amdgpu_dpm_enable_vce()
509 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable); in amdgpu_dpm_enable_vce()
515 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable) in amdgpu_dpm_enable_jpeg() argument
519 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable); in amdgpu_dpm_enable_jpeg()
525 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) in amdgpu_pm_load_smu_firmware() argument
527 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_pm_load_smu_firmware()
533 mutex_lock(&adev->pm.mutex); in amdgpu_pm_load_smu_firmware()
534 r = pp_funcs->load_firmware(adev->powerplay.pp_handle); in amdgpu_pm_load_smu_firmware()
541 *smu_version = adev->pm.fw_version; in amdgpu_pm_load_smu_firmware()
544 mutex_unlock(&adev->pm.mutex); in amdgpu_pm_load_smu_firmware()
548 int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable) in amdgpu_dpm_handle_passthrough_sbr() argument
552 if (is_support_sw_smu(adev)) { in amdgpu_dpm_handle_passthrough_sbr()
553 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_handle_passthrough_sbr()
554 ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle, in amdgpu_dpm_handle_passthrough_sbr()
556 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_handle_passthrough_sbr()
562 int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size) in amdgpu_dpm_send_hbm_bad_pages_num() argument
564 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_send_hbm_bad_pages_num()
567 if (!is_support_sw_smu(adev)) in amdgpu_dpm_send_hbm_bad_pages_num()
570 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_send_hbm_bad_pages_num()
572 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_send_hbm_bad_pages_num()
577 int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size) in amdgpu_dpm_send_hbm_bad_channel_flag() argument
579 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_send_hbm_bad_channel_flag()
582 if (!is_support_sw_smu(adev)) in amdgpu_dpm_send_hbm_bad_channel_flag()
585 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_send_hbm_bad_channel_flag()
587 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_send_hbm_bad_channel_flag()
592 int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, in amdgpu_dpm_get_dpm_freq_range() argument
602 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_dpm_freq_range()
605 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_dpm_freq_range()
606 ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle, in amdgpu_dpm_get_dpm_freq_range()
610 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_dpm_freq_range()
615 int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, in amdgpu_dpm_set_soft_freq_range() argument
620 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_set_soft_freq_range()
626 if (!is_support_sw_smu(adev)) in amdgpu_dpm_set_soft_freq_range()
629 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_soft_freq_range()
634 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_soft_freq_range()
639 int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev) in amdgpu_dpm_write_watermarks_table() argument
641 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_write_watermarks_table()
644 if (!is_support_sw_smu(adev)) in amdgpu_dpm_write_watermarks_table()
647 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_write_watermarks_table()
649 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_write_watermarks_table()
654 int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, in amdgpu_dpm_wait_for_event() argument
658 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_wait_for_event()
661 if (!is_support_sw_smu(adev)) in amdgpu_dpm_wait_for_event()
664 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_wait_for_event()
666 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_wait_for_event()
671 int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value) in amdgpu_dpm_set_residency_gfxoff() argument
673 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_set_residency_gfxoff()
676 if (!is_support_sw_smu(adev)) in amdgpu_dpm_set_residency_gfxoff()
679 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_residency_gfxoff()
681 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_residency_gfxoff()
686 int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value) in amdgpu_dpm_get_residency_gfxoff() argument
688 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_residency_gfxoff()
691 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_residency_gfxoff()
694 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_residency_gfxoff()
696 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_residency_gfxoff()
701 int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value) in amdgpu_dpm_get_entrycount_gfxoff() argument
703 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_entrycount_gfxoff()
706 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_entrycount_gfxoff()
709 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_entrycount_gfxoff()
711 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_entrycount_gfxoff()
716 int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) in amdgpu_dpm_get_status_gfxoff() argument
718 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_status_gfxoff()
721 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_status_gfxoff()
724 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_status_gfxoff()
726 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_status_gfxoff()
731 uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) in amdgpu_dpm_get_thermal_throttling_counter() argument
733 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_thermal_throttling_counter()
735 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_thermal_throttling_counter()
746 void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, in amdgpu_dpm_gfx_state_change() argument
749 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_gfx_state_change()
750 if (adev->powerplay.pp_funcs && in amdgpu_dpm_gfx_state_change()
751 adev->powerplay.pp_funcs->gfx_state_change_set) in amdgpu_dpm_gfx_state_change()
752 ((adev)->powerplay.pp_funcs->gfx_state_change_set( in amdgpu_dpm_gfx_state_change()
753 (adev)->powerplay.pp_handle, state)); in amdgpu_dpm_gfx_state_change()
754 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_gfx_state_change()
757 int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, in amdgpu_dpm_get_ecc_info() argument
760 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_ecc_info()
763 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_ecc_info()
766 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_ecc_info()
768 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_ecc_info()
773 struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, in amdgpu_dpm_get_vce_clock_state() argument
776 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_vce_clock_state()
782 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_vce_clock_state()
783 vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, in amdgpu_dpm_get_vce_clock_state()
785 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_vce_clock_state()
790 void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, in amdgpu_dpm_get_current_power_state() argument
793 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_current_power_state()
795 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_current_power_state()
798 *state = adev->pm.dpm.user_state; in amdgpu_dpm_get_current_power_state()
802 *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle); in amdgpu_dpm_get_current_power_state()
805 *state = adev->pm.dpm.user_state; in amdgpu_dpm_get_current_power_state()
808 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_current_power_state()
811 void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, in amdgpu_dpm_set_power_state() argument
814 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_power_state()
815 adev->pm.dpm.user_state = state; in amdgpu_dpm_set_power_state()
816 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_power_state()
818 if (is_support_sw_smu(adev)) in amdgpu_dpm_set_power_state()
821 if (amdgpu_dpm_dispatch_task(adev, in amdgpu_dpm_set_power_state()
824 amdgpu_dpm_compute_clocks(adev); in amdgpu_dpm_set_power_state()
827 enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev) in amdgpu_dpm_get_performance_level() argument
829 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_performance_level()
835 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_performance_level()
837 level = pp_funcs->get_performance_level(adev->powerplay.pp_handle); in amdgpu_dpm_get_performance_level()
839 level = adev->pm.dpm.forced_level; in amdgpu_dpm_get_performance_level()
840 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_performance_level()
845 int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev, in amdgpu_dpm_force_performance_level() argument
848 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_force_performance_level()
858 if (adev->pm.dpm.thermal_active) in amdgpu_dpm_force_performance_level()
861 current_level = amdgpu_dpm_get_performance_level(adev); in amdgpu_dpm_force_performance_level()
865 if (adev->asic_type == CHIP_RAVEN) { in amdgpu_dpm_force_performance_level()
866 if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) { in amdgpu_dpm_force_performance_level()
869 amdgpu_gfx_off_ctrl(adev, false); in amdgpu_dpm_force_performance_level()
872 amdgpu_gfx_off_ctrl(adev, true); in amdgpu_dpm_force_performance_level()
883 amdgpu_device_ip_set_powergating_state(adev, in amdgpu_dpm_force_performance_level()
886 amdgpu_device_ip_set_clockgating_state(adev, in amdgpu_dpm_force_performance_level()
892 amdgpu_device_ip_set_clockgating_state(adev, in amdgpu_dpm_force_performance_level()
895 amdgpu_device_ip_set_powergating_state(adev, in amdgpu_dpm_force_performance_level()
900 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_force_performance_level()
902 if (pp_funcs->force_performance_level(adev->powerplay.pp_handle, in amdgpu_dpm_force_performance_level()
904 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_force_performance_level()
908 adev->pm.dpm.forced_level = level; in amdgpu_dpm_force_performance_level()
910 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_force_performance_level()
915 int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, in amdgpu_dpm_get_pp_num_states() argument
918 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_pp_num_states()
924 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_pp_num_states()
925 ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, in amdgpu_dpm_get_pp_num_states()
927 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_pp_num_states()
932 int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, in amdgpu_dpm_dispatch_task() argument
936 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_dispatch_task()
942 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_dispatch_task()
943 ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, in amdgpu_dpm_dispatch_task()
946 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_dispatch_task()
951 int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) in amdgpu_dpm_get_pp_table() argument
953 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_pp_table()
959 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_pp_table()
960 ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle, in amdgpu_dpm_get_pp_table()
962 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_pp_table()
967 int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, in amdgpu_dpm_set_fine_grain_clk_vol() argument
972 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_fine_grain_clk_vol()
978 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_fine_grain_clk_vol()
979 ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, in amdgpu_dpm_set_fine_grain_clk_vol()
983 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_fine_grain_clk_vol()
988 int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, in amdgpu_dpm_odn_edit_dpm_table() argument
993 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_odn_edit_dpm_table()
999 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_odn_edit_dpm_table()
1000 ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, in amdgpu_dpm_odn_edit_dpm_table()
1004 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_odn_edit_dpm_table()
1009 int amdgpu_dpm_print_clock_levels(struct amdgpu_device *adev, in amdgpu_dpm_print_clock_levels() argument
1013 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_print_clock_levels()
1019 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_print_clock_levels()
1020 ret = pp_funcs->print_clock_levels(adev->powerplay.pp_handle, in amdgpu_dpm_print_clock_levels()
1023 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_print_clock_levels()
1028 int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, in amdgpu_dpm_emit_clock_levels() argument
1033 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_emit_clock_levels()
1039 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_emit_clock_levels()
1040 ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, in amdgpu_dpm_emit_clock_levels()
1044 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_emit_clock_levels()
1049 int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, in amdgpu_dpm_set_ppfeature_status() argument
1052 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_ppfeature_status()
1058 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_ppfeature_status()
1059 ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, in amdgpu_dpm_set_ppfeature_status()
1061 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_ppfeature_status()
1066 int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf) in amdgpu_dpm_get_ppfeature_status() argument
1068 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_ppfeature_status()
1074 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_ppfeature_status()
1075 ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, in amdgpu_dpm_get_ppfeature_status()
1077 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_ppfeature_status()
1082 int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, in amdgpu_dpm_force_clock_level() argument
1086 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_force_clock_level()
1092 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_force_clock_level()
1093 ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle, in amdgpu_dpm_force_clock_level()
1096 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_force_clock_level()
1101 int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev) in amdgpu_dpm_get_sclk_od() argument
1103 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_sclk_od()
1109 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_sclk_od()
1110 ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle); in amdgpu_dpm_get_sclk_od()
1111 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_sclk_od()
1116 int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) in amdgpu_dpm_set_sclk_od() argument
1118 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_sclk_od()
1120 if (is_support_sw_smu(adev)) in amdgpu_dpm_set_sclk_od()
1123 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_sclk_od()
1125 pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); in amdgpu_dpm_set_sclk_od()
1126 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_sclk_od()
1128 if (amdgpu_dpm_dispatch_task(adev, in amdgpu_dpm_set_sclk_od()
1131 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; in amdgpu_dpm_set_sclk_od()
1132 amdgpu_dpm_compute_clocks(adev); in amdgpu_dpm_set_sclk_od()
1138 int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev) in amdgpu_dpm_get_mclk_od() argument
1140 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_mclk_od()
1146 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_mclk_od()
1147 ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle); in amdgpu_dpm_get_mclk_od()
1148 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_mclk_od()
1153 int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) in amdgpu_dpm_set_mclk_od() argument
1155 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_mclk_od()
1157 if (is_support_sw_smu(adev)) in amdgpu_dpm_set_mclk_od()
1160 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_mclk_od()
1162 pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); in amdgpu_dpm_set_mclk_od()
1163 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_mclk_od()
1165 if (amdgpu_dpm_dispatch_task(adev, in amdgpu_dpm_set_mclk_od()
1168 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; in amdgpu_dpm_set_mclk_od()
1169 amdgpu_dpm_compute_clocks(adev); in amdgpu_dpm_set_mclk_od()
1175 int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, in amdgpu_dpm_get_power_profile_mode() argument
1178 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_power_profile_mode()
1184 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_power_profile_mode()
1185 ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, in amdgpu_dpm_get_power_profile_mode()
1187 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_power_profile_mode()
1192 int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, in amdgpu_dpm_set_power_profile_mode() argument
1195 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_power_profile_mode()
1201 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_power_profile_mode()
1202 ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, in amdgpu_dpm_set_power_profile_mode()
1205 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_power_profile_mode()
1210 int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table) in amdgpu_dpm_get_gpu_metrics() argument
1212 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_gpu_metrics()
1218 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_gpu_metrics()
1219 ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, in amdgpu_dpm_get_gpu_metrics()
1221 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_gpu_metrics()
1226 int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, in amdgpu_dpm_get_fan_control_mode() argument
1229 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_fan_control_mode()
1235 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_fan_control_mode()
1236 ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, in amdgpu_dpm_get_fan_control_mode()
1238 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_fan_control_mode()
1243 int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, in amdgpu_dpm_set_fan_speed_pwm() argument
1246 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_fan_speed_pwm()
1252 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_fan_speed_pwm()
1253 ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, in amdgpu_dpm_set_fan_speed_pwm()
1255 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_fan_speed_pwm()
1260 int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, in amdgpu_dpm_get_fan_speed_pwm() argument
1263 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_fan_speed_pwm()
1269 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_fan_speed_pwm()
1270 ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, in amdgpu_dpm_get_fan_speed_pwm()
1272 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_fan_speed_pwm()
1277 int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, in amdgpu_dpm_get_fan_speed_rpm() argument
1280 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_fan_speed_rpm()
1286 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_fan_speed_rpm()
1287 ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, in amdgpu_dpm_get_fan_speed_rpm()
1289 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_fan_speed_rpm()
1294 int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, in amdgpu_dpm_set_fan_speed_rpm() argument
1297 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_fan_speed_rpm()
1303 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_fan_speed_rpm()
1304 ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, in amdgpu_dpm_set_fan_speed_rpm()
1306 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_fan_speed_rpm()
1311 int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, in amdgpu_dpm_set_fan_control_mode() argument
1314 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_fan_control_mode()
1320 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_fan_control_mode()
1321 ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, in amdgpu_dpm_set_fan_control_mode()
1323 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_fan_control_mode()
1328 int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, in amdgpu_dpm_get_power_limit() argument
1333 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_power_limit()
1339 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_power_limit()
1340 ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle, in amdgpu_dpm_get_power_limit()
1344 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_power_limit()
1349 int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, in amdgpu_dpm_set_power_limit() argument
1352 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_power_limit()
1358 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_power_limit()
1359 ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle, in amdgpu_dpm_set_power_limit()
1361 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_power_limit()
1366 int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) in amdgpu_dpm_is_cclk_dpm_supported() argument
1370 if (!is_support_sw_smu(adev)) in amdgpu_dpm_is_cclk_dpm_supported()
1373 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_is_cclk_dpm_supported()
1374 cclk_dpm_supported = is_support_cclk_dpm(adev); in amdgpu_dpm_is_cclk_dpm_supported()
1375 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_is_cclk_dpm_supported()
1380 int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, in amdgpu_dpm_debugfs_print_current_performance_level() argument
1383 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_debugfs_print_current_performance_level()
1388 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_debugfs_print_current_performance_level()
1389 pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle, in amdgpu_dpm_debugfs_print_current_performance_level()
1391 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_debugfs_print_current_performance_level()
1396 int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, in amdgpu_dpm_get_smu_prv_buf_details() argument
1400 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_smu_prv_buf_details()
1406 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_smu_prv_buf_details()
1407 ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, in amdgpu_dpm_get_smu_prv_buf_details()
1410 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_smu_prv_buf_details()
1415 int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev) in amdgpu_dpm_is_overdrive_supported() argument
1417 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in amdgpu_dpm_is_overdrive_supported()
1418 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_is_overdrive_supported()
1420 if ((is_support_sw_smu(adev) && smu->od_enabled) || in amdgpu_dpm_is_overdrive_supported()
1421 (is_support_sw_smu(adev) && smu->is_apu) || in amdgpu_dpm_is_overdrive_supported()
1422 (!is_support_sw_smu(adev) && hwmgr->od_enabled)) in amdgpu_dpm_is_overdrive_supported()
1428 int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, in amdgpu_dpm_set_pp_table() argument
1432 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_pp_table()
1438 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_pp_table()
1439 ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle, in amdgpu_dpm_set_pp_table()
1442 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_pp_table()
1447 int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev) in amdgpu_dpm_get_num_cpu_cores() argument
1449 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_num_cpu_cores()
1451 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_num_cpu_cores()
1457 void amdgpu_dpm_stb_debug_fs_init(struct amdgpu_device *adev) in amdgpu_dpm_stb_debug_fs_init() argument
1459 if (!is_support_sw_smu(adev)) in amdgpu_dpm_stb_debug_fs_init()
1462 amdgpu_smu_stb_debug_fs_init(adev); in amdgpu_dpm_stb_debug_fs_init()
1465 int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, in amdgpu_dpm_display_configuration_change() argument
1468 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_display_configuration_change()
1474 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_display_configuration_change()
1475 ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle, in amdgpu_dpm_display_configuration_change()
1477 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_display_configuration_change()
1482 int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, in amdgpu_dpm_get_clock_by_type() argument
1486 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_clock_by_type()
1492 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_clock_by_type()
1493 ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, in amdgpu_dpm_get_clock_by_type()
1496 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_clock_by_type()
1501 int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, in amdgpu_dpm_get_display_mode_validation_clks() argument
1504 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_display_mode_validation_clks()
1510 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_display_mode_validation_clks()
1511 ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, in amdgpu_dpm_get_display_mode_validation_clks()
1513 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_display_mode_validation_clks()
1518 int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, in amdgpu_dpm_get_clock_by_type_with_latency() argument
1522 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_clock_by_type_with_latency()
1528 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_clock_by_type_with_latency()
1529 ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, in amdgpu_dpm_get_clock_by_type_with_latency()
1532 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_clock_by_type_with_latency()
1537 int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, in amdgpu_dpm_get_clock_by_type_with_voltage() argument
1541 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_clock_by_type_with_voltage()
1547 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_clock_by_type_with_voltage()
1548 ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, in amdgpu_dpm_get_clock_by_type_with_voltage()
1551 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_clock_by_type_with_voltage()
1556 int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, in amdgpu_dpm_set_watermarks_for_clocks_ranges() argument
1559 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_watermarks_for_clocks_ranges()
1565 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_watermarks_for_clocks_ranges()
1566 ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, in amdgpu_dpm_set_watermarks_for_clocks_ranges()
1568 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_watermarks_for_clocks_ranges()
1573 int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, in amdgpu_dpm_display_clock_voltage_request() argument
1576 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_display_clock_voltage_request()
1582 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_display_clock_voltage_request()
1583 ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, in amdgpu_dpm_display_clock_voltage_request()
1585 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_display_clock_voltage_request()
1590 int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, in amdgpu_dpm_get_current_clocks() argument
1593 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_current_clocks()
1599 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_current_clocks()
1600 ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle, in amdgpu_dpm_get_current_clocks()
1602 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_current_clocks()
1607 void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) in amdgpu_dpm_notify_smu_enable_pwe() argument
1609 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_notify_smu_enable_pwe()
1614 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_notify_smu_enable_pwe()
1615 pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle); in amdgpu_dpm_notify_smu_enable_pwe()
1616 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_notify_smu_enable_pwe()
1619 int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, in amdgpu_dpm_set_active_display_count() argument
1622 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_active_display_count()
1628 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_active_display_count()
1629 ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle, in amdgpu_dpm_set_active_display_count()
1631 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_active_display_count()
1636 int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, in amdgpu_dpm_set_min_deep_sleep_dcefclk() argument
1639 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_min_deep_sleep_dcefclk()
1645 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_min_deep_sleep_dcefclk()
1646 ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, in amdgpu_dpm_set_min_deep_sleep_dcefclk()
1648 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_min_deep_sleep_dcefclk()
1653 void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, in amdgpu_dpm_set_hard_min_dcefclk_by_freq() argument
1656 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_hard_min_dcefclk_by_freq()
1661 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_hard_min_dcefclk_by_freq()
1662 pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle, in amdgpu_dpm_set_hard_min_dcefclk_by_freq()
1664 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_hard_min_dcefclk_by_freq()
1667 void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, in amdgpu_dpm_set_hard_min_fclk_by_freq() argument
1670 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_hard_min_fclk_by_freq()
1675 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_hard_min_fclk_by_freq()
1676 pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle, in amdgpu_dpm_set_hard_min_fclk_by_freq()
1678 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_hard_min_fclk_by_freq()
1681 int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, in amdgpu_dpm_display_disable_memory_clock_switch() argument
1684 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_display_disable_memory_clock_switch()
1690 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_display_disable_memory_clock_switch()
1691 ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, in amdgpu_dpm_display_disable_memory_clock_switch()
1693 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_display_disable_memory_clock_switch()
1698 int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, in amdgpu_dpm_get_max_sustainable_clocks_by_dc() argument
1701 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_max_sustainable_clocks_by_dc()
1707 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_max_sustainable_clocks_by_dc()
1708 ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, in amdgpu_dpm_get_max_sustainable_clocks_by_dc()
1710 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_max_sustainable_clocks_by_dc()
1715 enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, in amdgpu_dpm_get_uclk_dpm_states() argument
1719 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_uclk_dpm_states()
1725 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_uclk_dpm_states()
1726 ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, in amdgpu_dpm_get_uclk_dpm_states()
1729 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_uclk_dpm_states()
1734 int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, in amdgpu_dpm_get_dpm_clock_table() argument
1737 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_dpm_clock_table()
1743 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_dpm_clock_table()
1744 ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, in amdgpu_dpm_get_dpm_clock_table()
1746 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_dpm_clock_table()